-
1
-
-
0036287655
-
Three-dimensional very thin stacked packaging technology for SiP
-
Y. Yano, T. Sugiyama, S. Ishihara, Y. Fukui, H. Juso, "Three-dimensional Very Thin Stacked Packaging Technology for SiP," in Proc. 52st Electronic Components and Technology Conference(ECTC), San Diego, California USA, May.2002, pp 1329-1334.
-
Proc. 52st Electronic Components and Technology Conference(ECTC), San Diego, California USA, May.2002
, pp. 1329-1334
-
-
Yano, Y.1
Sugiyama, T.2
Ishihara, S.3
Fukui, Y.4
Juso, H.5
-
2
-
-
0036297122
-
A nobel integrated passive substrate fabricated directly on an organic laminate for RF application
-
A. Okubora, et al, "A Nobel Integrated Passive Substrate Fabricated Directly on An Organic Laminate for RF application," in Proc. 52st Electronic Components and Technology Conference(ECTC), San Dieg, California USA, May.2002, pp 672-675.
-
Proc. 52st Electronic Components and Technology Conference(ECTC), San Dieg, California USA, May.2002
, pp. 672-675
-
-
Okubora, A.1
-
3
-
-
0038752234
-
Embedded capacitor formed on PWB for next generation package
-
Y. Horikawa, A. Takano, A. Rokugawa, T. Iizima, "Embedded Capacitor Formed on PWB for Next Generation Package," in Proc. International Conference on Electronics Packaging(ICEP), Tokyo, Japan, April, 2002, 140-144.
-
Proc. International Conference on Electronics Packaging(ICEP), Tokyo, Japan, April, 2002
, pp. 140-144
-
-
Horikawa, Y.1
Takano, A.2
Rokugawa, A.3
Iizima, T.4
-
4
-
-
1242283555
-
Development of PWB with capacitors for RF module application
-
[in Japanease]
-
Y. Shimada, K. Otsuka, Y. Hirata, "Development of PWB with Capacitors for RF Module Application" in Journal of Japan Institute of Electronics Packaging(JIEP), Vol.5, No.7, 2002, pp636-640 [in Japanease].
-
(2002)
Journal of Japan Institute of Electronics Packaging(JIEP)
, vol.5
, Issue.7
, pp. 636-640
-
-
Shimada, Y.1
Otsuka, K.2
Hirata, Y.3
-
5
-
-
0036448277
-
Investigation of fundamental technology for 3D assembly
-
K. Murayama, M. Higashi, M. Shimizu, "Investigation of Fundamental Technology for 3D Assembly," in Proc. International Symposium on Microelectronics(IMAPS), Denver, Colorado, September, 2002, pp. 348-353.
-
Proc. International Symposium on Microelectronics(IMAPS), Denver, Colorado, September, 2002
, pp. 348-353
-
-
Murayama, K.1
Higashi, M.2
Shimizu, M.3
-
6
-
-
0038414201
-
Development of plasma stress relief technology in wafer thinning process
-
[in Japanese]
-
K. Arita, T. Iwai, H.Haji, E. Nitta, Y. Koma "Development of plasma stress relief technology in wafer thinning process", in Proc. 11st Micro Electronics Sympo(MES)., Osaka, Japan, Oct. 2001, pp175-178 [in Japanese].
-
Proc. 11st Micro Electronics Sympo(MES)., Osaka, Japan, Oct. 2001
, pp. 175-178
-
-
Arita, K.1
Iwai, T.2
Haji, H.3
Nitta, E.4
Koma, Y.5
-
7
-
-
0036283275
-
Development of wafer thinning and double-sided bumping technologies for three-dimensional stacked LSI
-
M. Sunohara, T. Fujii, M. Hosino, H. Yonemura, M. Tomisaka, K. Takahashi, "Development of Wafer Thinning and Double-sided Bumping Technologies for Three-dimensional Stacked LSI," in Proc. 52st Electronic Components and Technology Conference(ECTC), San Diego, California USA, May.2002, pp 238-245.
-
Proc. 52st Electronic Components and Technology Conference(ECTC), San Diego, California USA, May.2002
, pp. 238-245
-
-
Sunohara, M.1
Fujii, T.2
Hosino, M.3
Yonemura, H.4
Tomisaka, M.5
Takahashi, K.6
-
8
-
-
0038414214
-
Development of ultra thin package
-
[in Japanease]
-
K. Murayama, M. Higashi, "Development of Ultra thin Package", in Proc, 10st Micro Electronics Sympo(MES)., Osaka, Japan, Oct. 2000, pp267-271. [in Japanease]
-
Proc, 10st Micro Electronics Sympo(MES)., Osaka, Japan, Oct. 2000
, pp. 267-271
-
-
Murayama, K.1
Higashi, M.2
-
9
-
-
0011926220
-
Superfine flip chip interconnections in 20μm-pitch
-
K. Tanida, et al, "Superfine Flip Chip Interconnections in 20μm-pitch," in Proc. International Conference on Electronics Packaging, Tokyo, Japan, April, 2002, 333-338.
-
Proc. International Conference on Electronics Packaging, Tokyo, Japan, April, 2002
, pp. 333-338
-
-
Tanida, K.1
-
10
-
-
0038414209
-
Ultra-sonic flip-chip interconnection technology of chip on chip
-
[in Japanease]
-
F. Ando, et al, "Ultra-Sonic Flip-Chip Interconnection Technology of Chip on Chip," in Proc, 12st Micro Electronics Sympo., Osaka, Japan, Oct. 2002, pp47-50 [in Japanease].
-
Proc, 12st Micro Electronics Sympo., Osaka, Japan, Oct. 2002
, pp. 47-50
-
-
Ando, F.1
|