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Volumn , Issue , 2007, Pages 992-999

Electrical characterization and design optimization of embedded chip in substrate cavities

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONIC EQUIPMENT; ELECTRONICS PACKAGING; MICROPROCESSOR CHIPS; MOBILE PHONES; OPTIMIZATION; PERSONAL COMPUTERS;

EID: 35348899435     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2007.373918     Document Type: Conference Paper
Times cited : (4)

References (7)
  • 2
    • 28344435928 scopus 로고    scopus 로고
    • Lim, S.K,Physical design for 3D system on package, Design & Test of Computers, IEEE, 22, Issue 6, Nov.-Dec. 2005 Page(s):532-539
    • Lim, S.K,"Physical design for 3D system on package", Design & Test of Computers, IEEE, Volume 22, Issue 6, Nov.-Dec. 2005 Page(s):532-539
  • 4
    • 35348862171 scopus 로고    scopus 로고
    • Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop, Intel Corporation, Bumpless Build-Up Layer Packaging, ASME, 2002
    • Steven N. Towle, Henning Braunisch, Chuan Hu, Richard D. Emery, and Gilroy J. Vandentop, Intel Corporation, "Bumpless Build-Up Layer Packaging", ASME, 2002
  • 6
    • 84962234558 scopus 로고    scopus 로고
    • Ostmann, A.; Neumann, A.; Weser, S.; Jung, E.; Bottcher, L.; Reichl, H.,Realization of a stackable package using chip in polymer technology. Polymers and Adhesives in Microelectronics and Photonics, 2nd International IEEE Conference on 23-26 June 2002 Page(s): 160-164
    • Ostmann, A.; Neumann, A.; Weser, S.; Jung, E.; Bottcher, L.; Reichl, H.,"Realization of a stackable package using chip in polymer technology". Polymers and Adhesives in Microelectronics and Photonics, 2nd International IEEE Conference on 23-26 June 2002 Page(s): 160-164


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.