10 GSamples/s, 4-bit, 1.2V, design-for-testability ADC and DAC in 0.13μm CMOS technology

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 416-419

  Liang, Sheng Chuan ^a   Huang, Ding Jyun ^a   Ho, Chen Kang ^a   Hong, Hao Chiao ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; DESIGN FOR TESTABILITY; DIGITAL ARITHMETIC; DIGITAL INTEGRATED CIRCUITS; FEEDBACK AMPLIFIERS; HYBRID COMPUTERS; NETWORKS (CIRCUITS); SIGNAL TO NOISE RATIO;

CURRENT-MODE LOGIC; SOLID-STATE CIRCUITS CONFERENCE;

MULTICARRIER MODULATION;

EID: 51349129627     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425719     Document Type: Conference Paper

References (8)

1. M. Ghoneima, Y. Ismail, M. Khellah, J. Tschanz, and V. De, "Serial-link bus: a low-power on-chip bus architecture," in Proc. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), 2005, pp. 541-546.
2. C.-K. K. Yang, V. Stojanovic, S. Modjtahedi, M. Horowitz, and W. Ellersick, "A serial-link transceiver based on 8GSample/s A/D and D/A converters in 0.25μm CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1684-1692, Nov. 2001.
3. J. Park, R. Sun, L. R. Carley, and C. P. Yue, "A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), vol. 2, 2006, pp. 1162-1165. [
4. J. Sonntag, J. Stonick, J. Gorecki1, B. Beale, and et al., "An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 um CMOS," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2002, pp. 363-366.
5. S. Galal and B. Razavi, "10-Gb/s limiting amplifier and Laser/modulator driver in 0.18-μm CMOS technology," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2138-2146, Dec. 2003.
6. J. M. Musicer and J. Rabaey, "MOS current mode logic for low power, low noise CORDIC computation in mixed-signal environments," in Proc. International Symposium on Low Power Electronics and Design, Jul. 2000, pp. 102-107.
7. W. P. Burleson, M. Ciesielski, F. Klass, and W. Liu, "Wave- pipelining: a tutorial and research survey,," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 6, no. 3, pp. 464-474, Sep. 1998.
8. A. V. den Bosch, M. Steyaert, and W. Sansen, "SFDR-bandwidth limitations for high speed high resolution current steering CMOS D/A converters," in Proc. IEEE International Conference on Electronics, Circuits, and Systems (ICECS), vol. 3, Sep. 1999, pp. 1193-1196.