An adaptive PAM-4 5 Gb/s backplane transceiver in 0.25 um CMOS

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2002, Pages 363-366

  Sonntag, Jeff ^a   Stonick, John ^a   Gorecki, James ^a   Beale, Bill ^a   Check, Bill ^a   Gong, Xue Mei ^a   Guiliano, Joe ^a   Lee, Kyong ^a   Lefferts, Bob ^a   Martin, David ^a   Moon, Un Ku ^a   Sengir, Amber ^a   Titus, Stephen ^a   Wei, Gu Yeon ^a   Weinlader, Dan ^a   Yang, Yaohua ^a  

^a Accelerant Networks   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL TO ANALOG CONVERSION; EQUALIZERS; PULSE AMPLITUDE MODULATION; ROUTERS; SWITCHING CIRCUITS; TELECOMMUNICATION TRAFFIC;

BACKPLANE TRANSCEIVERS;

TRANSCEIVERS;

EID: 0036045289     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 0.4mm CMOS 10 Gb/s 4-PAM pre-emphasis serial link transmitter
2. Transmitter equalization for 4 Gb/s signalling
3. Multi-level signalling