A 10-Gbps, 8-PAM parallel interface with crosstalk cancellation for future hard disk drive channel ICs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1162-1165

  Park, Jaejin ^a   Sun, Ruifeng ^a   Carley, L Richard ^a   Yue, C Patrick ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADJACENT CHANNELS; CIRCUIT COMPONENTS; CROSS-TALK CANCELLATION; CROSSTALK REDUCTION; DATA ENCODING; DIGITAL CMOS; ELECTROMAGNETIC INTERFERENCE; HARD DISK DRIVE; HARD DISKS; HIGH-SPEED; LOOK-AHEAD; NEW SYSTEM; OUTPUT DRIVERS; PARALLEL INTERFACES; PHASE INTERPOLATOR; SIMULATION RESULT; TEST LOGIC;

ASSOCIATIVE STORAGE; CROSSTALK; ELECTROMAGNETIC COMPATIBILITY; ELECTROMAGNETIC PULSE; HARD DISK STORAGE; INTERFACES (COMPUTER); PNEUMATIC DRIVES; PULSE AMPLITUDE MODULATION; TRANSCEIVERS;

PHASE INTERFACES;

EID: 39549105739     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464800     Document Type: Conference Paper

References (8)

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8. K. Farzan and D. A. Johns, "A CMOS 10-Gb/s Power-Efficient 4- PAM Transmitter," IEEE JSSC, vol.39, pp. 529-532, March 2004.