A high-speed low-complexity two-parallel radix-24 FFT/IFFT processor for UWB applications

2007 IEEE Asian Solid-State Circuits Conference, A-SSCC

Volumn , Issue , 2007, Pages 284-287

  Lee, Hanho ^a   Shin, Minhyeok ^a  

^a Inha University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

HIGH SPEEDS; LOW-COMPLEXITY; RADIX-2;

SPEED;

EID: 51349106941     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2007.4425686     Document Type: Conference Paper

References (10)

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6. 4 FFT Processor for MB-OFDM UWB Systems," IEEE Inter. Symp. on Circuits and Systems, pp. 4719-4722,
7. J-Y. Oh, M-S. Lim, "Fast Fourier Transform Algorithm for Low-Power and Area-Efficient Algorithm," IEICE Trans. Communications, vol. E89-B, no. 4, pp. 1425-1429, April 2006.
8. S-M. Kim, J-G. Chung, and K. K. Parhi, "Low Error Fixed-width CSD Multiplier with Efficient Sign Extension," IEEE Transactions on Circuits and Systems-II, vol. 50, no. 12, Dec. 2003.
9. L. Jia, Y. Gao, J. Isoaho, and H. Tenhunen, "A new VLSI-oriented FFT Algorithm and Implementation," Proc. 11th Annu. IEEE Int. ASIC Conf., pp. 337-341, Sept. 1998.
10. K.J. Cho, K.C. Lee, J.G. Chung, and K.K. Parhi, "Design of Low-error. Fixed-width Modified Booth Multiplier," IEEE Trans. Very Large Scale. Integr. (VLSI), vol.12, no.5, pp.522-531, May 2004