-
1
-
-
69149109577
-
Modelling SystemC scheduler by refinement
-
Sept
-
D. Cansell, D. Méry, and C. Proch. Modelling SystemC scheduler by refinement. In ISOLA, Sept. 2005.
-
(2005)
ISOLA
-
-
Cansell, D.1
Méry, D.2
Proch, C.3
-
3
-
-
0038788460
-
-
R. Drechsler and D. Groβe. Reachability analysis for formal verification of systemc. In DSD, pages 337-340. IEEE, Sept. 2002.
-
R. Drechsler and D. Groβe. Reachability analysis for formal verification of systemc. In DSD, pages 337-340. IEEE, Sept. 2002.
-
-
-
-
4
-
-
33646754677
-
SVL: A scripting language for compositional verification
-
Aug
-
H. Garavel and F. Lang. SVL: a scripting language for compositional verification. In FORTE, pages 377-392, Aug. 2001.
-
(2001)
FORTE
, pp. 377-392
-
-
Garavel, H.1
Lang, F.2
-
5
-
-
38149115280
-
-
H. Garavel, F. Lang, R. Mateescu, and W. Serwe. CADP 2006: A toolbox for the construction and analysis of distributed processes. In CAV, 4590 of LNCS, pages 158-163, July 2007.
-
H. Garavel, F. Lang, R. Mateescu, and W. Serwe. CADP 2006: A toolbox for the construction and analysis of distributed processes. In CAV, volume 4590 of LNCS, pages 158-163, July 2007.
-
-
-
-
7
-
-
67649107486
-
CheckSyC: An efficient property checker for RTL SystemC designs
-
May
-
D. Groβe and R. Drechsler. CheckSyC: an efficient property checker for RTL SystemC designs. In ISCAS, volume 4, pages 4167-4170, May 2005.
-
(2005)
ISCAS
, vol.4
, pp. 4167-4170
-
-
Groβe, D.1
Drechsler, R.2
-
10
-
-
51349128005
-
-
ISO-8807. Lotos, a formal description technique based on the temporal ordering of observational behaviour, 1989.
-
ISO-8807. Lotos, a formal description technique based on the temporal ordering of observational behaviour, 1989.
-
-
-
-
11
-
-
34047148417
-
Formal verification of SystemC designs using a petri-net based representation
-
Mar
-
D. Karlsson, P. Eles, and Z. Peng. Formal verification of SystemC designs using a petri-net based representation. In DATE, pages 1228-1233, Mar. 2006.
-
(2006)
DATE
, pp. 1228-1233
-
-
Karlsson, D.1
Eles, P.2
Peng, Z.3
-
12
-
-
33745134408
-
Formal verification of SystemC by automatic hardware/software partitioning
-
IEEE, July
-
D. Kroening and N. Sharygina. Formal verification of SystemC by automatic hardware/software partitioning. In MEMOCODE, pages 101-110. IEEE, July 2005.
-
(2005)
MEMOCODE
, pp. 101-110
-
-
Kroening, D.1
Sharygina, N.2
-
13
-
-
33749017914
-
LusSy: An open tool for the analysis of systems-on-a-chip at the transaction level
-
Sept
-
M. Moy, F. Maraninchi, and L. Maillet-Contoz. LusSy: an open tool for the analysis of systems-on-a-chip at the transaction level. Design Automation for Embedded Systems, 10(2-3):73-104, Sept. 2005.
-
(2005)
Design Automation for Embedded Systems
, vol.10
, Issue.2-3
, pp. 73-104
-
-
Moy, M.1
Maraninchi, F.2
Maillet-Contoz, L.3
-
14
-
-
51349151966
-
Formalizing TLM with communicating state machines
-
Sept
-
B. Niemann and C. Haubelt. Formalizing TLM with communicating state machines. In FDL, pages 285-292, Sept. 2006.
-
(2006)
FDL
, pp. 285-292
-
-
Niemann, B.1
Haubelt, C.2
-
16
-
-
47349087256
-
A schedulerless semantics of TLM models written in SystemC via translation into LOTOS
-
In FM, of, May
-
O. Ponsini and W. Serwe. A schedulerless semantics of TLM models written in SystemC via translation into LOTOS. In FM, volume 5014 of LNCS, May 2008.
-
(2008)
LNCS
, vol.5014
-
-
Ponsini, O.1
Serwe, W.2
-
17
-
-
51349087538
-
-
OSCI SystemC TLM 2.0, draft 2 for public review, 2007.
-
OSCI SystemC TLM 2.0, draft 2 for public review, 2007.
-
-
-
-
18
-
-
38149011269
-
-
C. Traulsen, J. Cornet, M. Moy, and F. Maraninchi. A SystemC/TLM semantics in Promela and its possible applications. In SPIN Workshop, pages 204-222, July 2007.
-
C. Traulsen, J. Cornet, M. Moy, and F. Maraninchi. A SystemC/TLM semantics in Promela and its possible applications. In SPIN Workshop, pages 204-222, July 2007.
-
-
-
-
19
-
-
34547349041
-
Formal techniques for SystemC verification
-
June
-
M. Y. Vardi. Formal techniques for SystemC verification. In DAC, pages 188-192, June 2007.
-
(2007)
DAC
, pp. 188-192
-
-
Vardi, M.Y.1
-
20
-
-
34548346286
-
LOTOS code generation for model checking of STBus based SoC: The STBus interconnect
-
IEEE, June
-
P. Wodey, G. Camarroque, R. Hersemeule, and J.-P. Cousin. LOTOS code generation for model checking of STBus based SoC: the STBus interconnect. In MEMOCODE, pages 204-213. IEEE, June 2003.
-
(2003)
MEMOCODE
, pp. 204-213
-
-
Wodey, P.1
Camarroque, G.2
Hersemeule, R.3
Cousin, J.-P.4
|