Checksyc: An efficient property checker for RTL systemc designs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 4167-4170

  Große, Daniel ^a   Drechsler, Rolf ^a  

^a UNIVERSITY OF BREMEN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

FUNCTIONAL BEHAVIORS; HARDWARE/SOFTWARE INTEGRATION; LEVELS OF ABSTRACTION; NEW DESIGN; SAT PROBLEMS; SATISFIABILITY PROBLEMS; SYSTEMC; SYSTEMC DESIGN; TEMPORAL PROPERTY;

LOGIC DESIGN;

EID: 67649107486     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1465549     Document Type: Conference Paper

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