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Volumn , Issue , 2008, Pages 658-663

Controllable parameters identification for high speed channel through signal-power integrity combined analysis

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER NETWORKS; ELECTRIC POWER TRANSMISSION; FLOW INTERACTIONS; MARINE BIOLOGY; OPTIMIZATION; POWER ELECTRONICS; SIGNAL PROCESSING; SPEED; TIME DOMAIN ANALYSIS;

EID: 51349101891     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2008.4550042     Document Type: Conference Paper
Times cited : (6)

References (15)
  • 1
    • 0033341231 scopus 로고    scopus 로고
    • Simultaneous switch noise and plane bounce for CMOS technology
    • Oct
    • Smith, L., "Simultaneous switch noise and plane bounce for CMOS technology," Electrical performance of Electronic Packaging, Oct. 1999, pp. 163-166.
    • (1999) Electrical performance of Electronic Packaging , pp. 163-166
    • Smith, L.1
  • 2
    • 0033319683 scopus 로고    scopus 로고
    • Frequency-dependent crosstalk simulation for on-chip interconnections
    • Deutsch, A., et al, "Frequency-dependent crosstalk simulation for on-chip interconnections," IEEE Trans-CPMT-B, Vol. 22, No. 3 (1999), pp. 292-308.
    • (1999) IEEE Trans-CPMT-B , vol.22 , Issue.3 , pp. 292-308
    • Deutsch, A.1
  • 3
    • 77954997377 scopus 로고    scopus 로고
    • Design of experiments on an EMC test chip for the interrogation of SI and EMC measures
    • May
    • M. Coenen, R. Derikx, "Design of experiments on an EMC test chip for the interrogation of SI and EMC measures," IEEE International Symposium on Electromagnetic Compatibility, Vol. 2, May. 2003, pp. 844-847.
    • (2003) IEEE International Symposium on Electromagnetic Compatibility , vol.2 , pp. 844-847
    • Coenen, M.1    Derikx, R.2
  • 4
    • 0242695808 scopus 로고    scopus 로고
    • An Accurate and Efficient Analysis Method for Mulit-Gb/s Chip-to-chip Signaling Schemes
    • June
    • B. K. Casper, M. Haycock, R. Mooney, "An Accurate and Efficient Analysis Method for Mulit-Gb/s Chip-to-chip Signaling Schemes," VLSI Circuits Symposium, pp. 54-57, June 2002.
    • (2002) VLSI Circuits Symposium , pp. 54-57
    • Casper, B.K.1    Haycock, M.2    Mooney, R.3
  • 5
    • 0034497749 scopus 로고    scopus 로고
    • A new methodology for simultaneous switching nosie simulation
    • Oct
    • J. Zhao, Q. Chen, "A new methodology for simultaneous switching nosie simulation," Electrical Performance of Electronic Packaging, Oct., 2000, pp. 155-158.
    • (2000) Electrical Performance of Electronic Packaging , pp. 155-158
    • Zhao, J.1    Chen, Q.2
  • 6
    • 51349153501 scopus 로고    scopus 로고
    • Speed2K and PowerSI user Guide - Sigrity Corporation.
    • Speed2K and PowerSI user Guide - Sigrity Corporation.
  • 7
    • 51349096641 scopus 로고    scopus 로고
    • SPICE-compatible transmission line modeling using synthesized broadband multi-port representations
    • Oct
    • M. J. Choi, J. Morsey, J. Ihm, A. C Cangellaris, "SPICE-compatible transmission line modeling using synthesized broadband multi-port representations," Electrical performance of Electronic Packaging, Oct. 2002, pp. 363-366.
    • (2002) Electrical performance of Electronic Packaging , pp. 363-366
    • Choi, M.J.1    Morsey, J.2    Ihm, J.3    Cangellaris, A.C.4
  • 8
    • 36349002964 scopus 로고    scopus 로고
    • Stability, Causality, and Passivity in Electrical Interconnect Models
    • Triverio, P., et al, "Stability, Causality, and Passivity in Electrical Interconnect Models," IEEE Trans-CPMT-B, Vol. 30, No. 4 (2007), pp. 795-808.
    • (2007) IEEE Trans-CPMT-B , vol.30 , Issue.4 , pp. 795-808
    • Triverio, P.1
  • 9
    • 34548157489 scopus 로고    scopus 로고
    • An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and Finite-Difference Time-Domain Techniques
    • Guo, W., et al, "An Integrated Signal and Power Integrity Analysis for Signal Traces Through the Parallel Planes Using Hybrid Finite-Element and Finite-Difference Time-Domain Techniques," IEEE Trans-CPMT-B, Vol. 30, No. 4 (2007), pp. 558-565.
    • (2007) IEEE Trans-CPMT-B , vol.30 , Issue.4 , pp. 558-565
    • Guo, W.1
  • 10
    • 10444243296 scopus 로고    scopus 로고
    • The effects of on-chip and package decoupling capacitors and an efficient ASIC decoupling methodology
    • June
    • th Electronic Components and Technology Conf, June. 2004, pp. 556-567.
    • (2004) th Electronic Components and Technology Conf , pp. 556-567
    • Na, N.1
  • 13
    • 0004276254 scopus 로고    scopus 로고
    • Courier Dover Publications, pp
    • Germund Dahlquist, et al, Numerical Methods, Courier Dover Publications, pp. 163.
    • Numerical Methods , pp. 163
    • Dahlquist, G.1
  • 14
    • 0032139262 scopus 로고    scopus 로고
    • PRIMA: Passive reduced-order interconnect macromodeling algorithm
    • Aug
    • Odabasioglu, A., Celik, M., and Pileggi, L.T., "PRIMA: Passive reduced-order interconnect macromodeling algorithm," IEEE Trans. Computer-Aided Design, Vol. 17, No. 8, Aug. 1998, pp. 645-653.
    • (1998) IEEE Trans. Computer-Aided Design , vol.17 , Issue.8 , pp. 645-653
    • Odabasioglu, A.1    Celik, M.2    Pileggi, L.T.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.