The verification of the on-chip COMA cache coherence protocol

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 5140 LNCS, Issue , 2008, Pages 413-429

  Vu, Thuy Duong ^a   Zhang, Li ^b   Jesshope, Chris ^b  

^a Sectie Software Engineering

^b UNIVERSITY OF AMSTERDAM   (Netherlands)

Author keywords

Abstract state machine; Location consistency; On chip COMA cache coherence protocol; Verification

Indexed keywords

ABSTRACT STATE MACHINE; LOCATION CONSISTENCY; ON CHIPS; ON-CHIP COMA CACHE COHERENCE PROTOCOL; VERIFICATION;

COMPUTER NETWORKS; MATRIX ALGEBRA; SILICON; TECHNOLOGY;

NETWORK ARCHITECTURE;

EID: 51049116878     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-79980-1_31     Document Type: Conference Paper

References (16)

1. Bershad, B., Zekauskas, M., Sawdon, W.: The Midway distributed shared memory system. In: Proceedings of the IEEE COMPCON (1993)
2. Blumofe, R.D., Frigo, M., Joerg, C.F., Leiserson, C.E., Randall, K.H.: An analysis of DAG-consistent distributed shared-memory algorithms. In: Proceedings og the 18th Annual ACM Symposium on Parallel Algorithms and Architectures, pp. 297-308 (1996)
3. Bolychevsky, A., Jesshope, C.R., Muchnick, V.: Dynamic sheduling in rics architectures. IEE Proceedings Computers and Digital Techniques 143(5), 309-317 (1996)
4. Bousias, K., Hasasneh, N.M., Jesshope, C.R.: Instruction-level parallelism through Microthreading-a scalable Approach to chip multiprocessors. The Computer Journal 49 (2), 211-233 (2006)
5. Corporation. K.s.r.: Ksrl technical summary. Technical report (1992)
6. Gao, G.R., Sarkar, V.: Location consistency: Stepping beyond memory coherence barrier. In: Int'l Conf. Parallel Processing, vol. 2, pp. 73-76 (1995)
7. Gao, G.R., Sarkar, V.: Location consistency - A new memory model and cache consistency protocol. IEEE Transactions on Computers 49(8), 798-813 (2000)
8. Gharachorloo, K., Lenoski, D., Laudon, J., Gibbons, P., Gupta, A., Hennessy, J.: Memory consistency and event ordering in scalable shared-memory multiprocessors. In: Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 15-26 (1990)
9. Gurevich, Y.: Elvolving algebras 1993: Lipari guide. In: Börger, E. (ed.) Specification and Validation Methods, pp. 9-36. Oxford University Press, Oxford (1995)
10. Gurevich, Y.: May 1997 draft of the asm guide. Technical Report CSE-TR-336-97, EECS Department, University of Michigan (1997)
11. Hennessy, J.H., Patterson, D. A.: Computer Architecture: A Quantitative Approach (2006)
12. Jesshope, C.R.: Microthreading a model for distributed instruction-level concurrency. Parallel Processing Letters 16 (2), 209-228 (2006)
13. Jesshope, C.R., Luo, B.: Micro-threading: A new approach to future rise. In: ACAC 2000, pp. 31-41. IEEE Computer Society Press, Los Alamitos (2000)
14. Keleher, P., Cox, A.L., Zwaenpoel, W.: Lazy release consistency for software distributed shared memory. In: Proceedings of the 29th Annual International Symposium on Computer Architecture, pp. 13-21 (1992)
15. Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Transactions on Computers 28(9). 690-691 (1979)
16. Zhang, L., Jesshope, C.R.: On-chip coma cache-coherence protocol for microgrids of microthreaded cores. In: Euro-Par 2007 Workshops: Parallel Processing, vol. 4854, pp. 38-48. Springer, Heidelberg (2008)