-
2
-
-
0004185241
-
-
Adam Hilger Ltd ISBN 0-85274-811-6, ISBN 0-85274-812-4 (Pbk)
-
R W Hockney and C R Jesshope (1988) Parallel Computers 2, Adam Hilger Ltd ISBN 0-85274-811-6, ISBN 0-85274-812-4 (Pbk).
-
(1988)
Parallel Computers
, vol.2
-
-
Hockney, R.W.1
Jesshope, C.R.2
-
3
-
-
0026407190
-
A comparative study of automatic vectorizingcompilers
-
D Levine, D Callahan and J Dongarra (1991) A comparative study of automatic vectorizingcompilers, Parallel Computing 17 (10-11): 1223-1244.
-
(1991)
Parallel Computing
, vol.17
, Issue.10-11
, pp. 1223-1244
-
-
Levine, D.1
Callahan, D.2
Dongarra, J.3
-
4
-
-
0019577159
-
Programming with a high degree of parallelism in FORTRAN
-
C R Jesshope (1982) Programming with a high degree of parallelism in FORTRAN, Comp. Phys.Comm., 26, pp237-246.
-
(1982)
Comp. Phys.Comm.
, vol.26
, pp. 237-246
-
-
Jesshope, C.R.1
-
6
-
-
0021481310
-
The transputer
-
P Mattos (1984) The transputer, New Electronics, 17 (16) August 1984, pp4345.
-
(1984)
New Electronics
, vol.17
, Issue.16 AUGUST 1984
, pp. 4345
-
-
Mattos, P.1
-
7
-
-
0023439637
-
The IMS T800 transputer
-
M Homewood, D May, D Shepherd and R. Shepherd (1987) The IMS T800 Transputer, IEEE Micro, October 1987, pp10-26.
-
(1987)
IEEE Micro
, vol.OCTOBER 1987
, pp. 10-26
-
-
Homewood, M.1
May, D.2
Shepherd, D.3
Shepherd, R.4
-
8
-
-
33746200198
-
The Japanese earth simulator: A challenge and an opportunity
-
C Lazou (2002) The Japanese Earth Simulator: a challenge and an opportunity, Primeur monthly, http://www.hoise.com/primeur/02/articles/monthly/ CL-PR-06-02-1.html
-
(2002)
Primeur Monthly
-
-
Lazou, C.1
-
10
-
-
35048847997
-
Design of an 8-wide superscalar RISC microprocessor with simultaneousmultithreading
-
R P Peterson et. al. (2002) Design of an 8-wide superscalar RISC microprocessor with simultaneousmultithreading, ISSC Digest and Visuals Supplement.
-
(2002)
ISSC Digest and Visuals Supplement
-
-
Peterson, R.P.1
-
11
-
-
0033717865
-
Clock rate versus IPC: The end of the road for conventional microarchictectures
-
June, 2000
-
V Agarwal, H S Murukkathampoondi, S W Keckler, and D C Burger (2000) Clock rate versus IPC: The end of the road for conventional microarchictectures, Proc 27th International Symposium on ComputerArchitecture (ISCA), June, 2000.
-
(2000)
Proc 27th International Symposium on ComputerArchitecture (ISCA)
-
-
Agarwal, V.1
Murukkathampoondi, H.S.2
Keckler, S.W.3
Burger, D.C.4
-
12
-
-
41349090027
-
Reducing register ports for higher speed and lower energy
-
ACM ISBN ISSN: 1072-4451, 0-7695-1859-1
-
I Par, M Powell and T Vijaykumar (2002) Reducing register ports for higher speed and lower energy, Proc. 35th annual ACM/IEEE international symposium on Microarchitecture, pp 171-182, ACM ISBN ISSN: 1072-4451, 0-7695-1859-1
-
(2002)
Proc. 35th Annual ACM/IEEE International Symposium on Microarchitecture
, pp. 171-182
-
-
Par, I.1
Powell, M.2
Vijaykumar, T.3
-
14
-
-
33746200193
-
Topology optimization of interconnection networks
-
July 2005
-
A. Gupta and W. J. Dally (2005) Topology Optimization of Interconnection Networks, Computer Architecture Letters, Volume 4, July 2005.
-
(2005)
Computer Architecture Letters
, vol.4
-
-
Gupta, A.1
Dally, W.J.2
-
15
-
-
3242815471
-
Scaling to the end of silicon with EDGE architectures
-
July, 2004
-
D. Burger, S.W. Keckler, K.S. McKinley, et al. (2004) Scaling to the End of Silicon with EDGE Architectures, IEEE Computer, 37 (7), pp. 44-55, July, 2004.
-
(2004)
IEEE Computer
, vol.37
, Issue.7
, pp. 44-55
-
-
Burger, D.1
Keckler, S.W.2
McKinley, K.S.3
-
16
-
-
33746198362
-
Threads on the cheap: Multithreaded execution in a WaveCache processor
-
at June 2004
-
S. Swanson, A. Schwerin, A. Petersen, M. Oskin and S. Eggers (2004) Threads on the Cheap: Multithreaded Execution in a WaveCache Processor, Proc WCED in conjunction with ISCA, at June 2004.
-
(2004)
Proc WCED in Conjunction with ISCA
-
-
Swanson, S.1
Schwerin, A.2
Petersen, A.3
Oskin, M.4
Eggers, S.5
-
17
-
-
4644353790
-
Evaluation of the raw microprocessor: An exposed-wire-delay architecture for ILP and streams
-
June 2004
-
M. Bedford Taylor, W. Lee, J. Miller, et. al. (2004) Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams, Proc ISCA, June 2004.
-
(2004)
Proc ISCA
-
-
Taylor, M.B.1
Lee, W.2
Miller, J.3
-
18
-
-
0030232590
-
Dynamic scheduling in RISC architectures
-
A Bolychevsky, C R Jesshope and V B Muchnick, (1996) Dynamic scheduling in RISC architectures, IEE Trans. E, Computers and Digital Techniques, 143, pp309-317.
-
(1996)
IEE Trans. E, Computers and Digital Techniques
, vol.143
, pp. 309-317
-
-
Bolychevsky, A.1
Jesshope, C.R.2
Muchnick, V.B.3
-
19
-
-
35248832488
-
Multithreaded microprocessors evolution or revolution
-
Omondo and Sedukhin (Eds.), Springer, LNCS2823 (Berlin, Germany), ISSN0302-9743, Aizu, Japan, 22-26 Sept 2003
-
C R Jesshope (2003) Multithreaded microprocessors evolution or revolution, Proc. ACSAC 2003: Advances in Computer Systems Architecture, Omondo and Sedukhin (Eds.), pp 21-45, Springer, LNCS2823 (Berlin, Germany), ISSN0302-9743, Aizu, Japan, 22-26 Sept 2003.
-
(2003)
Proc. ACSAC 2003: Advances in Computer Systems Architecture
, pp. 21-45
-
-
Jesshope, C.R.1
-
20
-
-
33644893333
-
Instruction-level parallelism through Microthreading - A scalable Approach to chip multiprocessors
-
K. Bousias, N. M. Hasasneh and C. R. Jesshope (2006) Instruction-level parallelism through Microthreading - a scalable Approach to chip multiprocessors, The Computer Journal, 49 (2),pp211-233.
-
(2006)
The Computer Journal
, vol.49
, Issue.2
, pp. 211-233
-
-
Bousias, K.1
Hasasneh, N.M.2
Jesshope, C.R.3
-
21
-
-
33746208065
-
-
Computer Journal, 49 (2) pp211-233.
-
Computer Journal
, vol.49
, Issue.2
, pp. 211-233
-
-
-
22
-
-
33746198354
-
DanSoft develops VLIW design
-
L Gwennap (1997) DanSoft develops VLIW design. Microproc. Report, 11, 2 (Feb. 17), 1822.
-
(1997)
Microproc. Report
, vol.11
, Issue.2 FEB. 17
, pp. 1822
-
-
Gwennap, L.1
-
23
-
-
0042850375
-
Correlation prefetching with a user-LevelMemory thread
-
Y Solihin, J Lee and J Torrellas, (2003) Correlation Prefetching with a User-LevelMemory Thread, IEEE Trans. on Parallel and Distributed Systems, vol. 14, no. 6.
-
(2003)
IEEE Trans. on Parallel and Distributed Systems
, vol.14
, Issue.6
-
-
Solihin, Y.1
Lee, J.2
Torrellas, J.3
-
25
-
-
0032662989
-
Simultaneous subordinate microthreading (SSMT)
-
R Chappell, J Stark, S Kim, S Reinhardt, and Y Patt (1999) Simultaneous subordinate microthreading (SSMT), Proc. Intl. Symposium on Computer Architecture.
-
(1999)
Proc. Intl. Symposium on Computer Architecture
-
-
Chappell, R.1
Stark, J.2
Kim, S.3
Reinhardt, S.4
Patt, Y.5
-
30
-
-
0036267893
-
Multithreaded Processors
-
British Computer Society
-
T Ungerer, B Robic and J Silc, M (2002) Multithreaded Processors, The Computer Journal, 45 (3), pp320-348, British Computer Society.
-
(2002)
The Computer Journal
, vol.45
, Issue.3
, pp. 320-348
-
-
Ungerer, T.1
Robic, B.2
Silc, J.3
-
31
-
-
0242551617
-
Single assignment C - Efficient support for high-level array operations in a functional setting
-
S-B Scholz (2003) Single Assignment C - Efficient Support for High-Level Array Operations in a Functional Setting, Journal of Functional Programming, 13(6), pp1005-1059.
-
(2003)
Journal of Functional Programming
, vol.13
, Issue.6
, pp. 1005-1059
-
-
Scholz, S.-B.1
-
32
-
-
33746208002
-
Microgrids and micro-contexts: Support structures for microthread scheduling and synchronisation
-
to be published in [?] (Amsterdam, July 2005)
-
Bell, I, Hasasneh, N and Jesshope C R (2005) Microgrids and Micro-contexts: Support Structures for Microthread Scheduling and Synchronisation, to be published in [?] (Special issue and Proc. 1st MicroGrid Conference, Amsterdam, July 2005). Preprint located at: http://staff.science. uva.nl/jesshope/Papers/IJPP.pdf.
-
(2005)
Special Issue and Proc. 1st MicroGrid Conference
-
-
Bell, I.1
Hasasneh, N.2
Jesshope, C.R.3
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