On-chip COMA cache-coherence protocol for microgrids of microthreaded cores

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4854 LNCS, Issue , 2008, Pages 38-48

  Zhang, Li ^a   Jesshope, Chris ^b  

^a UNIVERSITY OF AMSTERDAM   (Netherlands)

^b NONE   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTS COMMUNICATION; MICROTHREADED CORES;

ABSTRACTING; IDENTIFICATION (CONTROL SYSTEMS); MATHEMATICAL MODELS; SCHEDULING;

NETWORK PROTOCOLS;

EID: 41549112893     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-78474-6_7     Document Type: Conference Paper

References (16)

1. Mercaldi, M., Swanson, S., Petersen, A., Putnam, A., Schwerin, A., Oskin, M., Eggers, S.J.: Instruction scheduling for a tiled dataflow architecture. In: ASPLOS-XII: Proceedings of the 12th international conference on Architectural support for programming languages and operating systems, pp. 141-150. ACM Press, New York (2006)
2. Burger, D., Keckler, S.W., McKinley, K.S., Dahlin, M., John, L.K., Lin, C., Moore, C.R., Burrill, J., McDonald, R.G., Yoder, W.: The TRIPS Team: Scaling to the end of silicon with edge architectures. Computer 37(7), 44-55 (2004)
3. Jesshope, C.R.: A model for the design and programming of multicores. In: Advances in Parallel Computing, IOS Press, Amsterdam (Draft paper submitted, 2007)
4. Tullsen, D.M., Lo, J.L., Eggers, S.J., Levy, H.M.: Supporting fine-grained synchronization on a simultaneous multithreading processor. In: HPCA 1999: Proceedings of the 5th International Symposium on High Performance Computer Architecture, Washington, DC, USA, p. 54 (1999)
5. Gao, G.R., Sarkar, V.: Location consistency-a new memory model and cache consistency protocol. IEEE Transactions on Computers 49(8), 798-813 (2000)
6. Wulf, W.A., McKee, S.A.: Hitting the memory wall: implications of the obvious. SIGARCH Comput. Archit. News 23(1), 20-24 (1995)
7. Besedin. D.: Testing platforms with rightmark memory analyzer benchmark, part 5: Intel pentium m platform (dothan) (May 2004), http://www.digit-life.com/ articles2/rmma/rmma-dothan.html
8. Intel Corporation: Intel develops tera-scale research chips (September 2006), http://www.intel.com/go/terascale/
9. Corporation, K.S.R.: Ksr1 technical summary. Technical report (1992)
10. Dahlgren, F., Torrellas, J.: Cache-only memory architectures. Computer 32(6), 72-79 (1999)
11. LeBlanc, T.J., Marsh, B.D., Scott, M.L.: Memory management for large-scale numa multiprocessors. Technical report, Rochester, NY, USA (1989)
12. Hagersten, E., Landin, A., Haridi, S.: DDM - a cache-only memory architecture. IEEE Computer 25(9), 44-54 (1992)
13. Lamport, L.: How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Computers 28(9), 690-691 (1979)
14. Gharachorloo, K., Lenoski, D., Laudon, J., Gibbons, P.B., Gupta, A., Hennessy, J.L.: Memory consistency and event ordering in scalable shared-memory multiprocessors. In: 25 Years ISCA: Retrospectives and Reprints, pp. 376-387 (1998)
15. Dill. D.L.: The murphi verification system. In: Alur, R.. Henzinger, T.A. (eds.) CAV 1996. LNCS, vol. 1102, pp. 390-393. Springer, Heidelberg (1996)
16. Pong, F., Dubois, M.: Verification techniques for cache coherence protocols. ACM Computing Surveys 29(1), 82-126 (1997)