Noncomplementary BiCMOS logic and CMOS logic for low-voltage, low-power operation - A comparative study

IEEE Journal of Solid-State Circuits

Volumn 33, Issue 10, 1998, Pages 1580-1585

  Margala, Martin ^a   Durdle, Nelson G ^a  

^a UNIVERSITY OF ALBERTA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; ELECTRIC INVERTERS; LOGIC DESIGN; MOSFET DEVICES;

POWER-DELAY PRODUCT;

CMOS INTEGRATED CIRCUITS;

EID: 0032188191     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.720409     Document Type: Review

References (12)

1. J. M. Rabaey and M. Pedram, Eds., Low Power Design Methodologies. Norwell, MA: Kluwer, 1996.
2. J. M. Rabaey, Digital Integrated Circuits. Eglewood Cliffs, NJ: Prantice-Hall, 1996.
3. R. Y. V. Chik and C. A. T. Salima, "Design of a 1.5 V full-swing bootstrapped BiCMOS logic circuit," IEEE J. Solid-State Circuits, vol. 30, pp. 972-978, Sept. 1995.
4. S. H. K. Embabi, A. Bellaouar, and K. Islam, "A bootstrapped bipolar CMOS (B2CMOS) gate for low-voltage applications," IEEE J. Solid-State Circuits, vol. 30, pp. 47-53, Jan 1995.
5. A. Bellaouar, M. I. Elmasry, and S. H. K. Embabi, "Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime," IEEE J. Solid-State Circuits, vol. 30, pp. 629-636, June 1995.
6. Y. K. Seng and S. S. Rofail, "1.1 V high speed, low power BiCMOS logic circuit," Electron. Lett., vol. 31, no. 13, pp. 1039-1041, 22nd June 1995.
7. A. H. M. Shousha, "Low-voltage full-swing noncomplementary BiC-MOS buffers," in Proc. 7th Mediterranean Electrotechnical Conf. (Melecon), 1994, vol. 2, pp. 541-544.
8. J. B. Kuo, K. W. Su, J. H. Lou, S. S. Chen, and C. S. Chiang, "A 1.5 V full-swing BiCMOS dynamic logic gate suitable for VLSI using low-voltage BiCMOS technology," IEEE J. Solid-State Circuits, vol. 30, pp. 73-75, Jan. 1995.
9. M. Suzuki, N. Ohkubo, T. Shinbo, T. Yamanaka, A. Shimizu, K. Sasaki, and Y. Nakagome, "A 1.7-ns 32-b CMOS ALU in double pass-transistor logic," IEEE J. Solid-State Circuits, vol. 28, pp. 1145-1151, Nov. 1993.
10. J. M. Wang, S. C. Fang, and W. S. Feng, "New efficient designs for XOR and XNOR functions on the transistor level," IEEE J. Solid-State Circuits, vol. 29, pp. 780-786, July 1994.
11. S. S. Lee and M. Ismail, "1.5 V full-swing BiCMOS dynamic logic circuits," IEEE Trans. Circuits Syst. I, vol. 43, pp. 760-768, Sept. 1996.
12. P. A. Raje, K. C. Saraswat, and K. M. Cham, "A new methodology for design of BiCMOS gates and comparison with CMOS," IEEE Trans. Electron Devices, vol. 39, pp. 339-347, Feb. 1992.