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Volumn , Issue , 2007, Pages 189-190

Highly reliable power aware memory design

Author keywords

[No Author keywords available]

Indexed keywords

HAMMING CODES; INTERNATIONAL (CO); MEAN TIME-TO-FAILURE (MTTF); MEMORY ARCHITECTURE(MA); MEMORY DESIGNS; ON CHIPS; ON LINE TESTING; POWER SAVINGS; POWER-AWARE;

EID: 46749094220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2007.37     Document Type: Conference Paper
Times cited : (1)

References (11)
  • 1
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  • 3
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    • Multi-level memory systems using error control codes
    • Chang et. al, "Multi-level memory systems using error control codes", ISCAS04, pp.393-396.
    • ISCAS04 , pp. 393-396
    • Chang1    et., al.2
  • 4
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    • http://www.public.itrs.org
  • 5
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    • Trends in low-power RAM circuit technologies
    • April
    • K. Itoh et.al, "Trends in low-power RAM circuit technologies" , IEEE Proc., vol. 83, pp524-543, April 1995
    • (1995) IEEE Proc , vol.83 , pp. 524-543
    • Itoh, K.1
  • 6
    • 0022733598 scopus 로고
    • Power reduction in megabit DRAM's
    • June
    • Kimura et al, "Power reduction in megabit DRAM's", IEEE J. Solid state circuits, vol.21, pp. 381-389, June 1986.
    • (1986) IEEE J. Solid state circuits , vol.21 , pp. 381-389
    • Kimura1
  • 7
    • 0024121998 scopus 로고    scopus 로고
    • An on-chip double-bit error-correcting code for three-dimensional dynamic random-access memory
    • P. Mazumder, "An on-chip double-bit error-correcting code for three-dimensional dynamic random-access memory", ITC88, pp.279-288.
    • ITC88 , pp. 279-288
    • Mazumder, P.1
  • 8
    • 46749149087 scopus 로고    scopus 로고
    • LPRAM A novel LowPower High-Performance RAM design with testability and Scalability
    • S. Bhattacharjee and D. K. Pradhan, "LPRAM A novel LowPower High-Performance RAM design with testability and Scalability", IEEE TC, vol. 23, no. 5, 2004.
    • (2004) IEEE TC , vol.23 , Issue.5
    • Bhattacharjee, S.1    Pradhan, D.K.2
  • 9
    • 15044363155 scopus 로고    scopus 로고
    • Robust System Design with Built-in Soft-Error Resilience
    • Feb
    • S. Mitra et al., "Robust System Design with Built-in Soft-Error Resilience" , IEEE computer society Vol. 38, No. 2 pp. 43-52 , Feb. 2005
    • (2005) IEEE computer society , vol.38 , Issue.2 , pp. 43-52
    • Mitra, S.1
  • 10
    • 46749117428 scopus 로고    scopus 로고
    • Multiple Upsets Tolerance in SRAM Memory, ISCAS07, May 2007
    • to appear
    • Costas Argyrides, H.R. Zarandi, D.K. Pradhan, "Multiple Upsets Tolerance in SRAM Memory," ISCAS07, May 2007. (to appear)
    • Costas Argyrides, H.R.1    Zarandi, D.K.P.2
  • 11
    • 84943817322 scopus 로고
    • Error Detecting and Error Correcting Codes
    • April
    • R.W. Hamming "Error Detecting and Error Correcting Codes" The Bell System Technical Journal, Vol 26, No 2, April 1950. pp147-160
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    • Hamming, R.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.