Analysing the effect of process variation to reduce parametric yield loss

Proceedings - 2008 IEEE International Conference on Integrated Circuit Design and Technology, ICICDT

Volumn , Issue , 2008, Pages 171-175

  Ramakrishnan, H ^a,b   Shedabale, S ^a,b   Russell, G ^a,b   Yakovlev, A ^a,b  

^a IEEE

^b NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

DFM; RSM; Strained silicon; Variability; Yield

Indexed keywords

ELECTRIC CONDUCTIVITY; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS INDUSTRY; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MONTE CARLO METHODS; PROCESS ENGINEERING; SEMICONDUCTOR MATERIALS; TECHNOLOGY;

CIRCUIT PERFORMANCES; COMPUTATIONAL OVERHEADS; DFM; HIGH VOLUME PRODUCTS; INTEGRATED CIRCUIT DESIGN; INTERNATIONAL CONFERENCES; MARKET DEMANDS; MONTE CARLO APPROACH; MONTE-CARLO ANALYSIS; MUTUAL EXCLUSIONS; PARAMETRIC YIELD LOSS; PROCESS OPTIMISATION; PROCESS PARAMETERS; PROCESS VARIATIONS; PRODUCT LIFETIME; RESPONSE SURFACES; RSM; SEMICONDUCTOR MANUFACTURERS; STATISTICAL TOOLS; STRAINED SILICON; VARIABILITY; YIELD;

DESIGN OF EXPERIMENTS;

EID: 50849138734     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICICDT.2008.4567272     Document Type: Conference Paper

References (24)

1. B. P. Wong, A. Mittal, Y. Cao, and G. Starr., "Nano - CMOS circuit and physical design", Wiley Inter-Science, 1" Ed. 2005, New Jersey.
2. S.Tirumala, Y.Mahotin, X.Lin, V.Moroz, L.Smith, S.Krishnamurthy, L.Bomholt, and D.Pramanik, "Bringing Manufacturing into Design via Process-Dependent SPICE Models" 7th International Symposium on Quality Electronic Design, 2006 (ISQED '06), Mar. 2006.
3. C. Jacoboni, and P.Lugli, "The Monte Carlo method for semiconductor device simulation", Springer, 1" Ed. 1989, New York.
4. X. Gan, and A. J. Walton., "A comparison of direct Monte Carlo and DOE simulations for optimising IC processes," Int. Conf. Solid state and Integrated circuit technology, pp. 616-618, Oct. 1995.
5. Boning, D. and P. Mozumder, "DOE/Opt: A System for Design of Experiments, Response Surface Modeling, and Optimization using Process and Device Simulation," IEEE Trans. Semi. Manuf., pp. 233-244, Jan. 1994
6. th Ed. 2001.
7. R. L. Plackett, and J. P. Burman., " The design of optimum multifactorial experiments," Biometrika, Vol.33, pp. 305-325, 1946.
8. TSUPREM4 user's manual: Two-Dimensional Process simulation program, Sunnyvale, CA: Synopsys, Inc., 2000.
9. MEDICI, user's manual: Two-Dimensional. Device simulation program, Sunnyvale, CA: Synopsys, Inc., 2000.
10. AURORA user guide: AURORA simulation program, Sunnyvale, CA: Synopsys, Inc., 2006.
11. PSPICE user's manual: ORCAD PCB design suite., Ver.10.5. Cadence design systems Inc San Jode, CA.
12. Minitab, "Minitab Release 15, Statistical Software," Minitab Inc., 2006.
13. A.M. Abas, A. Bystrov, D.J. Kinniment, O.V. Maevsky, G. Russell and A.V. Yakovlev, "Time Difference Amplifier," IEEE Elec. Lett., 38, no.23, pp. 1437-1438, Nov. 2002.
14. J. Zhou, D. Kinniment, O. Russell, and A. Yakovlev, " A Robust Synchronizer," Proc. Emerging VLSI Tech. and Arch. (ISVLSI), pp. 442-443, 2006.
15. C. Dike, and E. Burton, "Miller and Noise effects in a syncronizing flip flop, " IEEE J. Solid state circuits., Vol. 34, no.6, pp. 849-855, Jun. 1999.
16. M. T. Currie, C. W. Leitz, T. A. Langdo, O. Taraschi, and E. A. Fitzgerald, "Carrier mobilities and process stability of strained-Si n. and p-MOSFETs on. SiGe virtual substrates," J. Vac. Sci. Technol.B, Microelectron. Process. Phenom, Vol. 19, pp. 2268-2279, Nov. 2001.
17. S. Chattopadhyay, L. S. Driscoll, K. S. K. Kwa, S. H. Olsen, and A. G. O'Neill, "Strained-Si MOSFETs on relaxed SiGe platforms: Performance and challenges," Solid State Electron., Vol. 48, pp. 1407-1416, Aug. 2004.
18. K. Rim, J. L. Hoyt, and J. F. Gibbons, "Fabrication and analysis of deep submicron s-Si n-MOSFET's", IEEE Trans. Electron Devices, Vol. 47, no. 7, pp. 1406-1415, Jul. 2000.
19. H. Ramakrishnan, K. Maharatna, S. Chattopadhyay, and A. Yakovlev, "Impact of strain on the design of low-power high-speed circuits," ISCAS 2007, pp. 1153-1156, New Orleans, May. 2007.
20. H. Ramakrishnan, S. Chattopadhyay, K. Maharatna, and A. Yakovlev, "Exploration of potential of strained silicon CMOS for low-power circuit design", Int. Conf. on Ultimate Integration on. Silicon (ULIS), pp. 29-32, Mar. 2007
21. Model for assessment of cmos technologies and roadmaps (MASTAR), ST Microelectronics, Advanced devices research group, 2000-2005.
22. International Technology Roadmap for Semiconductors, http://public.itrs. net, 2005.
23. L. Yang, J. R. Watling, R. C. W. Wilkins, M. Borici, J. R. Barker, A. Asenov, and S. Roy, "Si/SiGe heterostructure parameters for device simulations", Semicond. Sci. Technol., Vol. 19, pp. 1174-11.82, Aug. 2004.
24. S. Shedabale, S. Chattopadhyay, H. Ramakrishnan, S Uppal, A.Yakovlev, and A.G. O'Neill,"Statitical Analysis and Variability Modelling for 0.3um n-MOS Si Process", PGC 2007, Newcastle University, Jan 2007.