A robust synchronizer

Proceedings - IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures 2006

Volumn 2006, Issue , 2006, Pages 442-443

  Zhou, Jun ^a   Kinniment, David ^a   Russell, Gordon ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; SYNCHRONIZATION; THERMAL EFFECTS;

JAMB LATCH; LATCH CIRCUIT DESIGNS; LOW VOLTAGE SYNCHRONIZERS;

VOLTAGE CONTROL;

EID: 33749362681     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2006.12     Document Type: Conference Paper

References (2)

1. C.Dike and E.Burton. "Miller and Noise Effects in a Synchronizing Flip-Flop". IEEE Journal of Solid State Circuits Vol. 34 No. 6, pp.849-855, June 1999
2. R. L. Cline. "Method and circuit for improving metastable resolving time in low-power multi-state devices" US patent 5,789,945, February 27, 1996