-
2
-
-
0035392814
-
Coverage metrics for functional validation of hardware designs
-
Jul-Aug
-
S. Tasiran, K. Keutzer, Coverage metrics for functional validation of hardware designs. Design & Test of Computers, IEEE, Volume 18, Issue 4, Jul-Aug. 2001, Pages 36-45.
-
(2001)
Design & Test of Computers, IEEE, Volume 18, Issue
, vol.4
, pp. 36-45
-
-
Tasiran, S.1
Keutzer, K.2
-
3
-
-
45549103953
-
Systematic Mistake Analysis of Digital Computer Programs
-
J. C. Miller, C. J. Maloney, Systematic Mistake Analysis of Digital Computer Programs. Communications of the ACM, 1963, Pages 58-63.
-
(1963)
Communications of the ACM
, pp. 58-63
-
-
Miller, J.C.1
Maloney, C.J.2
-
5
-
-
0033700096
-
Back-tracing and Event-driven Techniques in High-level Simulation with Decision Diagrams
-
R. Ubar, J. Raik, A. Morawiec, Back-tracing and Event-driven Techniques in High-level Simulation with Decision Diagrams. ISCAS 2000, Vol. 1, pp. 208-211.
-
(2000)
ISCAS
, vol.1
, pp. 208-211
-
-
Ubar, R.1
Raik, J.2
Morawiec, A.3
-
7
-
-
0033719467
-
Fast Test Generation for Sequential Circuits Using Decision Diagrams Representations
-
Kluwer Academic Publisher
-
J. Raik, R. Ubar, Fast Test Generation for Sequential Circuits Using Decision Diagrams Representations. Journal of Electronic Testing: Theory and Applications 16, Kluwer Academic Publisher, 2000, pp. 213-226.
-
(2000)
Journal of Electronic Testing: Theory and Applications
, vol.16
, pp. 213-226
-
-
Raik, J.1
Ubar, R.2
-
8
-
-
0022769976
-
Graph-based algorithms for boolean function manipulation
-
R. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, C-35, 8:677-691, 1986
-
(1986)
IEEE Transactions on Computers
, vol.C-35
, Issue.8
, pp. 677-691
-
-
Bryant, R.1
-
9
-
-
0027226610
-
High-Level Transformations for Minimizing Syntactic Variances
-
June
-
V. Chayakul, D. D. Gajski, L. Ramachandran, "High-Level Transformations for Minimizing Syntactic Variances", Proc. of ACM/IEEE DAC, pp. 413-418, June 1993.
-
(1993)
Proc. of ACM/IEEE DAC
, pp. 413-418
-
-
Chayakul, V.1
Gajski, D.D.2
Ramachandran, L.3
-
10
-
-
0033681620
-
Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams
-
I. Ghosh, M. Fujita, "Automatic Test Pattern Generation for Functional RTL Circuits Using Assignment Decision Diagrams", Proc. of ACM/IEEE DAC, pp. 43-48, 2000.
-
(2000)
Proc. of ACM/IEEE DAC
, pp. 43-48
-
-
Ghosh, I.1
Fujita, M.2
-
11
-
-
0242303066
-
Efficient Sequential ATPG for Functional RTL Circuits
-
L. Zhang, I. Ghosh, M. Hsiao, "Efficient Sequential ATPG for Functional RTL Circuits", Int. Test Conf., pp.290-298, 2003.
-
(2003)
Int. Test Conf
, pp. 290-298
-
-
Zhang, L.1
Ghosh, I.2
Hsiao, M.3
-
12
-
-
50649120571
-
-
ITC'99 benchmark homepage, [www] http://www.cerc.utexas.edu/itc99- benchmarks/bench.html
-
ITC'99 benchmark homepage, [www] http://www.cerc.utexas.edu/itc99- benchmarks/bench.html
-
-
-
-
13
-
-
0031638166
-
OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification
-
F. Fallah, S. Devadas, K. Keutzer. OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. Proc. Design Automation Conference, pp.152-157, 1998.
-
(1998)
Proc. Design Automation Conference
, pp. 152-157
-
-
Fallah, F.1
Devadas, S.2
Keutzer, K.3
|