Cycle-based simulation with decision diagrams

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 454-458

  Ubar, Raimund ^a   Morawiec, Adam ^b   Raik, Jaan ^a  

^a TALLINN UNIVERSITY OF TECHNOLOGY   (Estonia)

^b TIMA LABORATORY   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CYCLE-BASED SIMULATIONS; DECISION DIAGRAM; EFFICIENCY GAIN; EVENT-DRIVEN SIMULATIONS; FUNCTIONAL SIMULATIONS; SPEED UP; SYNCHRONOUS DIGITAL SYSTEM;

EXHIBITIONS; MULTIPROCESSING SYSTEMS;

DESIGN;

EID: 33645514915     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761165     Document Type: Conference Paper

References (8)

1. H. Gruenbacher, M. Khosravipour, G. Gridling: "Improving Simulation Efficiency by Hierarchical Abstraction Transformations", System Level Design Language Workshop, Lausanne, Switzerland, 1998
2. P. McGeer et al: "Fast Discrete Function Evaluation Using Decision Diagrams", ICCAD'95, pp 402-407
3. P. Ashar, S. Malik: "Fast Functional Simulation Using Branching Programs", ICCAD Conf, 1995, pp 408-412
4. Y. Luo, T. Wongsonegoro, A. Aziz: "Hybrid Techniques for Fast Functional Simulation", DAC 1998
5. S.P. Smith, J. Larson: "A High Performance VHDL Simulator with Integrated Switch and Primitive Modelling ", Computer HD Languages and their Applications, Elsevier, IFIP, 1990
6. R.Ubar. "Test Synthesis with Alternative Graphs.", IEEE DesignTest of Comput., Spring 1996, pp.48-57
7. J.Raik, R.Ubar. Sequential Circuit Test Generation Using Decision Diagram Models. Published in the same Proceedings.
8. R. Leveugle, R. Ubar. "Synthesis of DDs from Clock-Driven Multi-Process VHDL for Test Generation.", MIXDES'98, Lodz, Poland, June 1998, pp.353-358.