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Volumn , Issue , 2007, Pages 995-998

An FPGA implementation of a scalable network-on-chip based on the token ring concept

Author keywords

[No Author keywords available]

Indexed keywords

AGGLOMERATION; AGGREGATES; CHLORINE COMPOUNDS; DIESEL ENGINES; ELECTRIC NETWORK TOPOLOGY; TELECOMMUNICATION SYSTEMS;

EID: 50649098260     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2007.4511160     Document Type: Conference Paper
Times cited : (5)

References (15)
  • 1
    • 50649123788 scopus 로고    scopus 로고
    • A. Jantsch, H. Tenhunen, Eds, Norwell, MA: Kluwer
    • A. Jantsch, H. Tenhunen, Eds., "Networks-on-Chip", Norwell, MA: Kluwer, 2001.
    • (2001) Networks-on-Chip
  • 2
    • 0034848112 scopus 로고    scopus 로고
    • Route Packets, Not Wires: On-Chip Interconnection Networks
    • W. Dally, B. Towles, "Route Packets, Not Wires: On-Chip Interconnection Networks", in Proc. of DAC, pp. 684-689, 2001.
    • (2001) Proc. of DAC , pp. 684-689
    • Dally, W.1    Towles, B.2
  • 3
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan
    • L. Benini, G. De Micheli, "Networks on chips: A new SoC paradigm", IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 4
  • 5
    • 24144461667 scopus 로고    scopus 로고
    • Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
    • Aug
    • P. P. Pande, C. Grecu, M. Jones, A. Ivanov, R. Saleh, "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures", IEEE Trans. on Computers, vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
    • (2005) IEEE Trans. on Computers , vol.54 , Issue.8 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Jones, M.3    Ivanov, A.4    Saleh, R.5
  • 6
    • 84859967419 scopus 로고    scopus 로고
    • SPIN: A Scalable, Packet Switched, On-Chip Micro-network
    • A. Adriahantenaina, H. Charlery, A. Greiner and L. Mortiez, "SPIN: a Scalable, Packet Switched, On-Chip Micro-network", DATE'2003, p.70-73.
    • (2003) DATE , pp. 70-73
    • Adriahantenaina, A.1    Charlery, H.2    Greiner, A.3    Mortiez, L.4
  • 8
    • 27344456043 scopus 로고    scopus 로고
    • Aethereal Network on Chip: Concepts, Architectures, and Implementations
    • Sept./Oct
    • K. Goossens, J. Dielisson, A. Rãdulescu, "Aethereal Network on Chip: Concepts, Architectures, and Implementations", IEEE Design & Test of Computers, vol. 22, no. 5, pp. 414-421, Sept./Oct. 2005.
    • (2005) IEEE Design & Test of Computers , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielisson, J.2    Rãdulescu, A.3
  • 9
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes: A Network-on-Chip Architecture for gigascale Systems-on-Chip
    • D. Bertozzi, L. Benini, "Xpipes: A Network-on-Chip Architecture for gigascale Systems-on-Chip", IEEE Circuits and Systems Magazine, vol. 4, no. 2, pp. 18-31, 2004.
    • (2004) IEEE Circuits and Systems Magazine , vol.4 , Issue.2 , pp. 18-31
    • Bertozzi, D.1    Benini, L.2
  • 14
    • 50649113526 scopus 로고    scopus 로고
    • Xilinx Inc
    • Xilinx Inc. http://www.xilinx.com.
  • 15
    • 50649090518 scopus 로고    scopus 로고
    • High Capacity ATM Switch
    • U.S. Patent 5745486, Apr. 28
    • M.E. Beshai, E. A. Munter, "High Capacity ATM Switch", U.S. Patent 5745486, Apr. 28, 1998.
    • (1998)
    • Beshai, M.E.1    Munter, E.A.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.