-
1
-
-
84913396280
-
Conditional sum addition logic
-
June
-
J. Sklansky, "Conditional Sum Addition Logic," IRE Trans. Electronic Computers, vol. 9, no. 2 pp. 226-231, June 1960.
-
(1960)
IRE Trans. Electronic Computers
, vol.9
, Issue.2
, pp. 226-231
-
-
Sklansky, J.1
-
4
-
-
0031633593
-
The improvement of conditional sum adder for low power applications
-
K.-H. Cheng, S.-M. Chiang, and S.-W. Cheng, "The Improvement of Conditional Sum Adder for Low Power Applications," Proc. 11th Ann. IEEE Int'l Application Specific Integrated Circuits Conf., pp.131-134, 1998.
-
(1998)
Proc. 11th Ann. IEEE Int'l Application Specific Integrated Circuits Conf.
, pp. 131-134
-
-
Cheng, K.-H.1
Chiang, S.-M.2
Cheng, S.-W.3
-
5
-
-
0026923645
-
ELM-A fast addition algorithm discovered by a program
-
Sept.
-
P. Kelliher, R.M. Owens, M.J. Irwin, and T.-T. Hwang, "ELM-A Fast Addition Algorithm Discovered by a Program," IEEE Trans. Computers, vol. 41, no. 9, Sept. 1992.
-
(1992)
IEEE Trans. Computers
, vol.41
, Issue.9
-
-
Kelliher, P.1
Owens, R.M.2
Irwin, M.J.3
Hwang, T.-T.4
-
7
-
-
0142035620
-
High-performance adder circuit generators in parameterized structural VHDL
-
Technical Report No. 96/7, Integrated Systems Laboratory, ETH Zurich Aug.
-
H. Kunz and R. Zimmermann, "High-Performance Adder Circuit Generators in Parameterized Structural VHDL," Technical Report No. 96/7, Integrated Systems Laboratory, ETH Zurich Aug. 1996.
-
(1996)
-
-
Kunz, H.1
Zimmermann, R.2
-
8
-
-
0025519548
-
Fast multiplication without carry-propagate addition
-
Nov.
-
M.D. Ercegovac et al., "Fast Multiplication without Carry-Propagate Addition", IEEE Trans. Computers, vol. 39, no. 11, Nov. 1990.
-
(1990)
IEEE Trans. Computers
, vol.39
, Issue.11
-
-
Ercegovac, M.D.1
-
9
-
-
0030701035
-
VLSI implementation of a 200-Mhz 16×16 left-to-right carry-free multiplier in 0.35μm CMOS technology for next-generation DSPs
-
R.K. Kolagotla et al., "VLSI Implementation of a 200-Mhz 16×16 Left-to-Right Carry-Free Multiplier in 0.35μm CMOS Technology for Next-Generation DSPs", Proc. IEEE 1997 Custom Integrated Circuits Conf., pp. 469-472, 1997.
-
(1997)
Proc. IEEE 1997 Custom Integrated Circuits Conf.
, pp. 469-472
-
-
Kolagotla, R.K.1
-
10
-
-
0011986890
-
Optimal designs for multipliers and multiply-accumulators
-
Aug.
-
P.F. Stelling and V.G. Oklobdzija, "Optimal Designs for Multipliers and Multiply-Accumulators," Proc. 15th IMACS World Congress on Scientific Computation, Modeling, and Applied Mathematics, vol. 4, pp. 739-744, Aug. 1997.
-
(1997)
Proc. 15th IMACS World Congress on Scientific Computation, Modeling, and Applied Mathematics
, vol.4
, pp. 739-744
-
-
Stelling, P.F.1
Oklobdzija, V.G.2
-
11
-
-
0034215897
-
A high-speed booth encoded parallel multiplier design
-
July
-
W.-C. Yeh and C.-W. Jen, "A High-Speed Booth Encoded Parallel Multiplier Design," IEEE Trans. Computers, vol. 49, no. 7, pp. 692-701, July 2000.
-
(2000)
IEEE Trans. Computers
, vol.49
, Issue.7
, pp. 692-701
-
-
Yeh, W.-C.1
Jen, C.-W.2
-
12
-
-
0030264539
-
Area-time-power tradeoffs in parallel address
-
Oct.
-
C.N. Nagendra, M.J. Irwin, and R.M. Owens, "Area-Time-Power Tradeoffs in Parallel Address," IEEE Trans. Circuits and Systems XII: Analog and Digital Signal Processing, vol. 43, no. 10, Oct. 1996.
-
(1996)
IEEE Trans. Circuits and Systems XII: Analog and Digital Signal Processing
, vol.43
, Issue.10
-
-
Nagendra, C.N.1
Irwin, M.J.2
Owens, R.M.3
-
14
-
-
0020102009
-
A regular layout for parallel adders
-
Mar.
-
R.P. Brent and H.-T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. 31, no. 3, Mar. 1982.
-
(1982)
IEEE Trans. Computers
, vol.31
, Issue.3
-
-
Brent, R.P.1
Kung, H.-T.2
-
15
-
-
0142035619
-
-
Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corp., Mar.
-
Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corp., Mar. 1998.
-
(1998)
-
-
|