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Volumn 52, Issue 10, 2003, Pages 1233-1242

Generalized earliest-first fast addition algorithm

Author keywords

Carry lookahead; Carry propagation adder; Conditional sum; Final adder

Indexed keywords

ADDERS; CARRY LOGIC; DIGITAL COMPUTERS; MATHEMATICAL OPERATORS; SET THEORY;

EID: 0142134999     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1234522     Document Type: Article
Times cited : (7)

References (15)
  • 1
    • 84913396280 scopus 로고
    • Conditional sum addition logic
    • June
    • J. Sklansky, "Conditional Sum Addition Logic," IRE Trans. Electronic Computers, vol. 9, no. 2 pp. 226-231, June 1960.
    • (1960) IRE Trans. Electronic Computers , vol.9 , Issue.2 , pp. 226-231
    • Sklansky, J.1
  • 7
    • 0142035620 scopus 로고    scopus 로고
    • High-performance adder circuit generators in parameterized structural VHDL
    • Technical Report No. 96/7, Integrated Systems Laboratory, ETH Zurich Aug.
    • H. Kunz and R. Zimmermann, "High-Performance Adder Circuit Generators in Parameterized Structural VHDL," Technical Report No. 96/7, Integrated Systems Laboratory, ETH Zurich Aug. 1996.
    • (1996)
    • Kunz, H.1    Zimmermann, R.2
  • 8
    • 0025519548 scopus 로고
    • Fast multiplication without carry-propagate addition
    • Nov.
    • M.D. Ercegovac et al., "Fast Multiplication without Carry-Propagate Addition", IEEE Trans. Computers, vol. 39, no. 11, Nov. 1990.
    • (1990) IEEE Trans. Computers , vol.39 , Issue.11
    • Ercegovac, M.D.1
  • 9
    • 0030701035 scopus 로고    scopus 로고
    • VLSI implementation of a 200-Mhz 16×16 left-to-right carry-free multiplier in 0.35μm CMOS technology for next-generation DSPs
    • R.K. Kolagotla et al., "VLSI Implementation of a 200-Mhz 16×16 Left-to-Right Carry-Free Multiplier in 0.35μm CMOS Technology for Next-Generation DSPs", Proc. IEEE 1997 Custom Integrated Circuits Conf., pp. 469-472, 1997.
    • (1997) Proc. IEEE 1997 Custom Integrated Circuits Conf. , pp. 469-472
    • Kolagotla, R.K.1
  • 11
    • 0034215897 scopus 로고    scopus 로고
    • A high-speed booth encoded parallel multiplier design
    • July
    • W.-C. Yeh and C.-W. Jen, "A High-Speed Booth Encoded Parallel Multiplier Design," IEEE Trans. Computers, vol. 49, no. 7, pp. 692-701, July 2000.
    • (2000) IEEE Trans. Computers , vol.49 , Issue.7 , pp. 692-701
    • Yeh, W.-C.1    Jen, C.-W.2
  • 14
    • 0020102009 scopus 로고
    • A regular layout for parallel adders
    • Mar.
    • R.P. Brent and H.-T. Kung, "A Regular Layout for Parallel Adders," IEEE Trans. Computers, vol. 31, no. 3, Mar. 1982.
    • (1982) IEEE Trans. Computers , vol.31 , Issue.3
    • Brent, R.P.1    Kung, H.-T.2
  • 15
    • 0142035619 scopus 로고    scopus 로고
    • Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corp., Mar.
    • Passport 0.35 micron, 3.3 volt, Optimum Silicon SC Library, CB35OS142, Avant! Corp., Mar. 1998.
    • (1998)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.