An Algorithmic Approach for Generic Parallel Adders

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 734-740

  Liu, Jianhua ^a   Zhou, Shuo ^a   Zhu, Haikun ^a   Cheng, Chung Kuan ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY ADDITION; RIPPLE CARRY ADDERS; SPECIFIC MULTIPLIERS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CAPACITANCE; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; DELAY CIRCUITS; TOPOLOGY;

ADDERS;

EID: 0346148442     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. J. Hennesey and D. A. Patterson, Computer Architecture - A Quantitative Approach. San Mateo, CA: Morgan Kaufmann, 1990. Appendix A.
3. R. P. Brent and H. T. Kung, "A regular layout for parallel adder", IEEE Trans. Comput., Vol. C-31, no. 3, pp. 260-264, Mar. 1983.
4. P. M. Kogge and H. S. Stone, "A parallel algorithm for the efficient solution of a general class of recurrence equations", IEEE Trans. Comput., Vol. C-22, no. 8, pp. 786-793, Aug. 1973.
5. B. Sugla and D. A. Carlson, "Extreme Area-Time Tradeoffs in VLSI", IEEE Trans. Comput., Vol. 39, no. 2, pp. 251-257, Feb. 1990.
6. B. Parhami, Computer Arithmetic, New York, Oxford: Oxford University Press, 2000.
7. W. C. Yeh and C. W. Jen, "High-Speed Booth Encoded Parallel Multiplier Design", IEEE Trans. Comput., Vol.49, no. 7, pp. 692-701, Jul. 2000.
8. J.P. Fishburn, "A depth-decreasing heuristic for combinational logic; or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between", 27th ACM/IEEE Design Automation Conference Proceedings, pp.361-4, 1990.