New designs of signed multipliers

3rd International IEEE Northeast Workshop on Circuits and Systems Conference, NEWCAS 2005

Volumn 2005, Issue , 2005, Pages 259-262

  Mudassir, Rizwan ^a   El Razouk, H ^a   Abid, Z ^a  

^a UNIVERSITY OF WESTERN ONTARIO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ARRAYS; DELAY CIRCUITS; DESIGN FOR TESTABILITY; TOPOLOGY; TREES (MATHEMATICS);

ARRAY MULTIPLIERS; POWER CONSUMPTION; WALLACE MULTIPLIERS;

MULTIPLYING CIRCUITS;

EID: 33745776300     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NEWCAS.2005.1496746     Document Type: Conference Paper

References (7)

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2. Keshab K. Parhi, VLSI digital signal processing systems. John Wiley & Sons, 1999. (Second edition)
3. st International Conference on Computer Design (ICCD'03), October, 2003.
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6. th CCECE Conference, Saskatoon, Canada, May 2005.
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