Low power parallel multiplier design for DSP applications through coefficient optimization

Proceedings - 12th Annual IEEE International ASIC/SOC Conference

Volumn , Issue , 1999, Pages 286-290

  Hong, Sangjin ^a   Kim, Suhwan ^a   Papaefthymiou, Marios C ^a   Stark, Wayne E ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DESIGN; ELECTRIC LOSSES; ENERGY CONSERVATION; FAST FOURIER TRANSFORMS; SIGNAL PROCESSING;

CRITICAL PATHS; DIGITAL SIGNAL PROCESSING (DSP); DSP APPLICATION; LOW-POWER DISSIPATION; LOW-POWER PARALLEL MULTIPLIER; MULTIPLIER DESIGN; QUANTIZATION ERRORS; SUPPLY VOLTAGES;

DIGITAL SIGNAL PROCESSING;

EID: 84935000961     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASIC.1999.806521     Document Type: Conference Paper

References (4)

1. A. P. Chandrakashan and R. Btodcrsen, "Low Power Digital CMOS Design", Kluwer Academic Publisher, 1996.
2. N. Sankarayya, K. Roy, and D. Bhattacharya, "Algorithms for Low Power FIR Filter Realization Using Differential Coefficients," International Conference on VLSI Design, pp. 174-178, January 1997.
3. M. Mehendale, S, D. Sherlekar, and G. Venkatesh, "Coefficient Optimization for Low Power Realization of FIR Filters", IEEE Workshop on VLSI Signal Processing, Japan 1995.
4. II. Samueli, "An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients," IEEE Transactions on Circuits and Systems, pp. 1044-1047, vol. 36, no. 7, July 1989.