Fast and low power multiplier architecture

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1996, Pages 53-56

  Abu Shama, E ^a   Maaz, M B ^a   Bayoumi, M A ^a  

^a UNIVERSITY OF LOUISIANA AT LAFAYETTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; ALGORITHMS; CALCULATIONS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; DIGITAL ARITHMETIC; LOGIC GATES; OPTIMIZATION; PERFORMANCE; TREES (MATHEMATICS);

BINARY TREE NETWORKS; MULTIPLIER ARCHITECTURE;

MULTIPLYING CIRCUITS;

EID: 0030366281     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)