A novel architecture for low-power design of parallel multipliers

Proceedings - IEEE Computer Society Workshop on VLSI, WVLSI 2001

Volumn , Issue , 2001, Pages 149-154

  Fayed, A A ^a   Bayoumi, M A ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

arithmetic; Low power; Multipliers

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC POWER SUPPLIES TO APPARATUS; FREQUENCY MULTIPLYING CIRCUITS; METAL TESTING; RECONFIGURABLE HARDWARE; SPICE; VLSI CIRCUITS;

CLOCK GATING TECHNIQUES; DEVELOPMENT TOOLS; HSPICE SIMULATIONS; LOW POWER; NOVEL ARCHITECTURE; PARALLEL MULTIPLIERS; PRE-PROCESSING OPERATIONS; PROPOSED ARCHITECTURES;

PARALLEL ARCHITECTURES;

EID: 0009595286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWV.2001.923154     Document Type: Conference Paper

References (8)

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