-
1
-
-
26844543667
-
An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels
-
Tampa, Florida, pp, May 11-12
-
M.Z. Zhang, H.T. Ngo, A.R. Livingston, and V.K Asari, "An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels," IEEE Computer Society Proceedings of the International Symposium on VLSI - ISVLSI 2005, Tampa, Florida, pp. 303-304, May 11-12, 2005.
-
(2005)
IEEE Computer Society Proceedings of the International Symposium on VLSI - ISVLSI
, pp. 303-304
-
-
Zhang, M.Z.1
Ngo, H.T.2
Livingston, A.R.3
Asari, V.K.4
-
2
-
-
33646520961
-
Automatic Derivation and Implementation of Fast Convolution Algorithms,
-
PhD Dissertation, Drexel University
-
A. F. Breitzman, "Automatic Derivation and Implementation of Fast Convolution Algorithms," PhD Dissertation, Drexel University, 2003.
-
(2003)
-
-
Breitzman, A.F.1
-
3
-
-
33845209951
-
Parameterised Automated Generation of Convolvers Implemented in FPGAs,
-
PhD Dissertation, University of Mining and Mentallurgy
-
E. Jamro, "Parameterised Automated Generation of Convolvers Implemented in FPGAs," PhD Dissertation, University of Mining and Mentallurgy, 2001
-
(2001)
-
-
Jamro, E.1
-
4
-
-
0031639542
-
An Efficient Programmable 2-D Convolver Chip
-
May
-
H. M. Chang and M. H. Sunwoo, "An Efficient Programmable 2-D Convolver Chip," Proc. Of the 1998 IEEE Intl. Symp. on Circuits and Systems, ISCAS, part 2, pp. 429-432, May 1998.
-
(1998)
Proc. Of the 1998 IEEE Intl. Symp. on Circuits and Systems, ISCAS
, Issue.PART 2
, pp. 429-432
-
-
Chang, H.M.1
Sunwoo, M.H.2
-
5
-
-
0026287601
-
An Advanced Programmable 2-D Convolution for Real Time Image Processing
-
ISCAS, pp, January
-
V. Hecht, K. Ronner and P. Pirsch, "An Advanced Programmable 2-D Convolution for Real Time Image Processing," in Proc. Of IEEE Intl. Symp. on Circuits and Systems, ISCAS, pp. 1897-1900, January 1991.
-
(1991)
Proc. Of IEEE Intl. Symp. on Circuits and Systems
, pp. 1897-1900
-
-
Hecht, V.1
Ronner, K.2
Pirsch, P.3
-
6
-
-
0023383977
-
A Multiprocessor Architecture for 2-D Digital Filters
-
July
-
J. H. Kim and W. E. Alexander, "A Multiprocessor Architecture for 2-D Digital Filters," IEEE Trans. On Computer, vol. C-36, pp. 876-884, July 1987.
-
(1987)
IEEE Trans. On Computer
, vol.C-36
, pp. 876-884
-
-
Kim, J.H.1
Alexander, W.E.2
-
7
-
-
24144501728
-
Implementation of Image Processing Algorithms on FPGA Hardware,
-
MS Thesis, Vanderbilt University
-
A. E. Nelson "Implementation of Image Processing Algorithms on FPGA Hardware," MS Thesis, Vanderbilt University, 2000.
-
(2000)
-
-
Nelson, A.E.1
-
9
-
-
0032646902
-
Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing
-
September
-
B. Bosi and G. Bois, "Reconfigurable Pipelined 2-D Convolvers for Fast Digital Signal Processing," IEEE Trans. On Very Large Scale Integration (VLSI) Systems, vol 7, no. 3, pp. 299-308, September 1999.
-
(1999)
IEEE Trans. On Very Large Scale Integration (VLSI) Systems
, vol.7
, Issue.3
, pp. 299-308
-
-
Bosi, B.1
Bois, G.2
-
10
-
-
51849104093
-
Constant Coefficient Multiplication in FPGA Structures
-
Maastricht, The Netherlands, September 5-7
-
K. Wiatr, and E. Jamro, "Constant Coefficient Multiplication in FPGA Structures," IEEE Proc. of the 26th Euriomicro Conference, Maastricht, The Netherlands, vol. 1, pp. 252-259, September 5-7, 2000.
-
(2000)
IEEE Proc. of the 26th Euriomicro Conference
, vol.1
, pp. 252-259
-
-
Wiatr, K.1
Jamro, E.2
-
11
-
-
0024699067
-
An Improved Search Algorithm for the Design of Multiplier-less FIR Filters with Powers-of-Two Coefficients
-
July
-
H. Samueli, "An Improved Search Algorithm for the Design of Multiplier-less FIR Filters with Powers-of-Two Coefficients," IEE Trans. Circuits systems, pp. 1044-1047, July 1989.
-
(1989)
IEE Trans. Circuits systems
, pp. 1044-1047
-
-
Samueli, H.1
-
12
-
-
4544258837
-
Local search method for FIR filter coefficients synthesis
-
Perth, Australia, pp, January
-
Z. Ye and C. H. Chang, "Local search method for FIR filter coefficients synthesis," in Proc. 2nd IEEE Int. Workshop on Electronic Design, Test and Applications (DELTA-2004), Perth, Australia, pp. 255-260, January 2004.
-
(2004)
Proc. 2nd IEEE Int. Workshop on Electronic Design, Test and Applications (DELTA-2004)
, pp. 255-260
-
-
Ye, Z.1
Chang, C.H.2
-
13
-
-
0034998841
-
A Systematic Algorithm for the Design of Multiplier less FIR Filters
-
Sydney, Australia, pp, May 6-9
-
J. Yli-Kaakinen, and T. Saramäki, "A Systematic Algorithm for the Design of Multiplier less FIR Filters," Proc. IEEE Int. Symp. Circuits Syst., Sydney, Australia, pp. 185-188, May 6-9, 2001.
-
(2001)
Proc. IEEE Int. Symp. Circuits Syst
, pp. 185-188
-
-
Yli-Kaakinen, J.1
Saramäki, T.2
-
14
-
-
0020968794
-
A Two-Level Pipelined Systolic Array for Multidimensional Convolution
-
February
-
H. T. Kung, L. M. Ruane, and D. W. L. Yen, "A Two-Level Pipelined Systolic Array for Multidimensional Convolution," Image and Vision Computing, vol. 1, no. 1, pp. 30-36, February 1983.
-
(1983)
Image and Vision Computing
, vol.1
, Issue.1
, pp. 30-36
-
-
Kung, H.T.1
Ruane, L.M.2
Yen, D.W.L.3
-
16
-
-
33646521005
-
Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution
-
Springer-Verlag, Berlin Heidelberg, October
-
M.Z. Zhang, H.T. Ngo, V.K. Asan, "Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution," Lecture Notes in Computer Science,. Springer-Verlag, Berlin Heidelberg, vol. 3740, pp. 65-78, October 2005.
-
(2005)
Lecture Notes in Computer Science
, vol.3740
, pp. 65-78
-
-
Zhang, M.Z.1
Ngo, H.T.2
Asan, V.K.3
|