An efficient VLSI architecture for 2-D convolution with quadrant symmetric kernels

Proceedings - IEEE Computer Society Annual Symposium on VLSI - New Frontiers in VLSI

Volumn , Issue , 2005, Pages 303-304

  Zhang, Ming Z ^a   Ngo, Hau T ^a   Livingston, Adam R ^a   Asari, Vijayan K ^a  

^a Old Dominion University   (United States)

Author keywords

2 D convolution; Pipelined architecture; Symmetric kernel; Systolic architecture

Indexed keywords

2-D CONVOLUTION; PIPELINED ARCHITECTURE; SYMMETRIC KERNEL; SYSTOLIC ARCHITECTURE;

ADDERS; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; CONVOLUTION; DATA HANDLING; DATA STORAGE EQUIPMENT; IMAGE PROCESSING;

VLSI CIRCUITS;

EID: 26844543667     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2005.15     Document Type: Conference Paper

References (8)

1. H. T. Kung and S. W. Song, "A systolic 2-D Convolution Chip," in Proc. IEEE Comput. Soc. Workshop Comput. Architecture for Pattern Anal. And Image Database Management, pp. 159-160, 1981.
2. H. T. Kung, L. M. Ruane, and D. W. L. Yen, "A two-level pipelined systolic array for multidimensional convolution," Image and Vision Computing, vol. 1, no. l, pp. 30-36, Feb. 1983.
3. A. Wong, "A New Scalable Systolic Array Processor Architecture For Discrete Convolution", Master Thesis, University of Kentucky, 2003.
4. H. M. Chang and M. H. Sunwoo, "An Efficient Programmable 2-D Convolver Chip," in Proc. Of the 1998 IEEE International Symposium on Circuits and Systems. ISCAS, Part 2, pp. 429-432, May 1998.
5. V. Hecht, K. Ronner and P. Pirsch, "An Advanced Programmable 2-D Convolution for Real Time Image Processing," in Proc. Of IEEE International Symposium on Circuits and Systems, pp. 1897-1900, 1991.
6. J. H. Kim and W. E. Alexander, "A Multiprocessor Architecture for 2-D Digital Filters," IEEE Trans. On Comput., vol. C-36, pp. 876-884, July 1987.
7. A. E. Nelson, "Implementation of Image Processing Algorithms On FPGA Hardware", Master Thesis, University of Tennessee, May 2000.
8. B.Bosi and G. Bois, "Reconfigurable Pipelined 2-D Convolvers for fast Digital Signal Processing," IEEE Trans. On Very Large Scale Systems, vol 7, no. 3, pp. 299-308, Sept. 1999.