Design of an efficient multiplier-less architecture for multi-dimensional convolution

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 3740 LNCS, Issue , 2005, Pages 65-78

  Zhang, Ming Z ^a   Ngo, Hau T ^a   Asari, Vijayan K ^a  

^a Old Dominion University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; CONVOLUTION; DATA HANDLING; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL TECHNIQUES; SYSTOLIC ARRAYS;

CLOCK FREQUENCY; DEGREE OF ACCURACY; MULTIPLIER-LESS ARCHITECTURE;

COMPUTER ARCHITECTURE;

EID: 33646521005     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/11572961_7     Document Type: Conference Paper

References (18)

1. A. F. Breitzman, "Automatic Derivation and Implementation of Fast Convolution Algorithms," Thesis, Drexel University, 2003.
2. HARRIS semiconductor Inc., Digital Signal Processing, 1994.
3. H. T. Kung, L. M. Ruane, and D. W. L. Yen, "A Two-Level Pipelined Systolic Array for Multidimensional Convolution," Image and Vision Computing, vol. 1, no. 1, pp. 30-36, Feb. 1983.
4. A. Wong, "A New Scalable Systolic Array Processor Architecture for Discrete Convolu-tion," Thesis, University of Kentucky, 2003.
5. A. E. Nelson "Implementation of Image Processing Algorithms on FPGA Hardware," Thesis, Vanderbilt University, 2000.
6. C. Chou, S. Mohanakrishnan, J. Evans, "FPGA Implementation of Digital Filters," in Proc. ICSPAT, pp. 80-88, 1993.
7. H. M. Chang and M. H. Sunwoo, "An Efficient Programmable 2-D Convolver Chip," Proc. Of the 1998 IEEE Intl. Symp. on Circuits and Systems, ISCAS, part 2, pp. 429-432, May 1998.
8. K. Chen, "Bit-Serial Realizations of a Class of Nonlinear Filters Based on Positive Boo-lean Functions," IEEE Trans. On Circuits and Systems, vol. 36, no. 6, pp. 785-794, June 1989.
9. M. H. Sunwoo, S. K. Oh, "A Multiplierless 2-D Convolver Chip for Real-Time Image Processing," Journal of VLSI Signal Processing, vol. 38, no. 1, pp. 63-71, 2004.
10. B. Bosi and G. Bois, "Reconfigurable Pipelined 2-D Convolvers for fast Digital Signal Processing," IEEE Trans. On Very Large Scale Systems, vol 7, no. 3, pp. 299-308, Sept. 1999.
11. M. Moore, "A DSP-Based Real-Time Image Processing System," Proc. of the 6th Intl. Conf. on Signal Processing Applications and Technology, Boston, MA, pp. 1042-1046, August 1995.
12. J. H. Kim and W. E. Alexander, "A Multiprocessor Architecture for 2-D Digital Filters," IEEE Trans. On Computer, vol. C-36, pp. 876-884, July 1987.
13. M. Y. Dabbagh and W. E. Alexander, "Multiprocessor Implementation of 2-D Denomina-tor-Separable Digital Filters for Real-Time Processing," IEEE Trans. on Acoustics, Speech, and Signal Processing, vol. ASSP-37, pp. 872-881, June 1989.
14. K. Wiatr, E. Jamro, "Constant Coefficient Multiplication in FPGA Structures," Proc. of the 26th Euriomicro Conference, Maastricht, The Netherlands, vol. 1, pp. 252-259, Sept. 5-7, 2000.
15. W. J. Oh, Y. H. Lee, "Implementation of Programmable Multiplierless FIR Filters with Power-of-Two Coefficients," IEEE Trans. on Circuits and Systems - Part -Fundamental Theory and Applications, vol.42, no.8, pp. 553-556, 1995.
16. S. Samadi, H. Iwakura, and A. Nishihara, "Multiplierless and Hierarchical Structures for Maximally Flat Half-Band FIR Filters," IEEE Trans. Circuits Syst.-II: Analog and Digi-tal Signal Process, vol. 46, pp. 1225-1230, 1999.
17. J. Yli-kaakinen and T. Saramaki, "A Systematic Algorithm for the Design of Multiplier-less FIR Filters," Proc. IEEE Int. Symp. Circuits Syst., Sydney, Australia, vol. II, pp. 185-188, May 6-9, 2001.
18. M. Z. Zhang, H. T. Ngo, A. R. Livingston, and K. V. Asari, "An Efficient VLSI Architec-ture for 2-D Convolution with Quadrant Symmetric Kernels," IEEE Computer Society Proc. of the Intl. Symp. on VLSI - ISVLSI 2005, Tampa, Florida, pp. 303-304, May 11-12, 2005.