Residue number system for low-power DSP applications

Conference Record - Asilomar Conference on Signals, Systems and Computers

Volumn , Issue , 2007, Pages 1412-1416

  Cardarilli, Gian Carlo ^a   Nannarelli, Alberto ^b   Re, Marco ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

^b TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL SIGNAL PROCESSING; FIR FILTERS;

FIR FILTERING; LOW POWER DSP; NUMBER REPRESENTATION; POWER CONSUMPTION REDUCTION; RESIDUE NUMBER SYSTEM; TWO'S COMPLEMENTS;

NUMBERING SYSTEMS;

EID: 50249150258     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ACSSC.2007.4487461     Document Type: Conference Paper

References (11)

1. G.C. Cardarilli, A. Nannarelli and M. Re. "Reducing Power Dissipation in FIR Filters using the Residue Number System", Proc. of 43rd IEEE Midwest Symposium on Circuits and Systems, p. 320-323, Lansing, USA, Aug. 2000.
2. A. D'Amora, A. Nannarelli, M. Re and G.C. Cardarilli. "Reducing" Power Dissipation in Complex Digital Filters by using the Quadratic Residue Number System", Proc. of 34th Asilomar Conference on Signals, Systems, and Computers, p. 879-883, Asilomar Conference Grounds, California (USA), Nov. 2000.
3. A. Nannarelli, M. Re and G.C. Cardarilli. "Tradeoffs between Residue Number System and Traditional FIR Filters", Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), Vol. I I, p. 305-308, May 2001.
4. A. Del Re, A. Nannarolli, and M. Re. "Implementation of Digital Filters in Carry-Save Residue Number System", Proc. of 35th Asilomar Conference on Signals, Systems, and Computers, p. 1309-1313, Asilomar Hotel and Conference Grounds, Pacific Grove, California (USA), Nov. 2001.
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6. A. Nannarelli, G.C. Cardarilli, and M. Re. "Power-delay tradeoff in residue number system", Proc. of 2003 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. V, p. 413-416, May 2003.
7. G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Low Power Implementation of Polyphase Filters in Quadratic Residue Number System", Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS), Vol. I I, p. 725-728, May 2004.
8. G.C. Cardarilli, A. Del Re, A. Nannarelli and M. Re. "Low Power and Low Leakage Implementation of RNS FIR Filters", Proc. of 39th Asilomar Conference on Signals, Systems, and Computers, Asilomar Hotel and Conference Grounds, Pacific Grove, CA, USA. October 30 - November 2, 2005.
9. T. Stouraitis and V. Paliouras, "Considering the alternatives in Low-Power Design", in IEEE Circuits and Devices, July 2001.
10. N. Magen, A. Kolodny, U. Weiser and N. Shamir "Interconnect-power Dissipation in a Microprocessor", Proc. of SLIP'04, Paris, France, February 2004.
11. L. Shang, A.S. Kaviani and K. Bathala "Dynamic Power Consumption in Virtex-II FPGA Family", Proc. of FPGA'02, Monterey, California, USA, February, 2002.