Reducing power dissipation in FIR filters using the residue number system

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 2000, Pages 320-323

  Cardarilli, Gian Carlo ^a   Nannarelli, Alberto ^a   Re, Marco ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DIGITAL ARITHMETIC; MODULATION; MULTIMEDIA SYSTEMS; SIGNAL PROCESSING;

POWER DISSIPATION; RESIDUE NUMBER SYSTEM;

FIR FILTERS;

EID: 0034463373     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Vlsi implementation of very high-order fir filters
2. A residue to binary conversion algorithm for signed numbers
3. A new efficient architecture for binary to rns conversion
4. A vlsi architecture for analog-to-residue conversion
5. Low power signal processing architectures using residue arithmetic
6. Low-power digital filters using residue arithmetic
7. Low power realization of residue number system based fir filters
8. Low-power division: Comparison among implementations of radix 4, 8 and 16
9. Clustered voltage scaling technique for low-power design