-
1
-
-
3843088398
-
-
Orain S et al. FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding. Thermal and mechanical simulation and experiments in microelectronics and microsystems. In: Proceedings of the EuroSimE; 2004. p. 47-52.
-
Orain S et al. FEM-based method to determine mechanical stress evolution during process flow in microelectronics. Application to stress-voiding. Thermal and mechanical simulation and experiments in microelectronics and microsystems. In: Proceedings of the EuroSimE; 2004. p. 47-52.
-
-
-
-
2
-
-
33751248750
-
-
Fiori V, Verrier S, et al. Thermo-mechanical modelling of process induced stress: layout effect on stress voiding phenomena. In: Eighth international works. Stress induced. Phenomena AIP; 2006. p. 254-61.
-
Fiori V, Verrier S, et al. Thermo-mechanical modelling of process induced stress: layout effect on stress voiding phenomena. In: Eighth international works. Stress induced. Phenomena AIP; 2006. p. 254-61.
-
-
-
-
3
-
-
0041692468
-
Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures
-
Dalleau D., Weide-Zaage K., and Danto Y. Simulation of time depending void formation in copper, aluminum and tungsten plugged via structures. Microelectron Reliab 43 (2003) 1821-1826
-
(2003)
Microelectron Reliab
, vol.43
, pp. 1821-1826
-
-
Dalleau, D.1
Weide-Zaage, K.2
Danto, Y.3
-
4
-
-
0142186254
-
Stationary and dynamic analysis of failure locations and void formation in interconnects due to the different migration mechanisms
-
Weide-Zaage K., Dalleau D., and Yu X. Stationary and dynamic analysis of failure locations and void formation in interconnects due to the different migration mechanisms. Mater Sci Semicond Process 6 (2003) 85-92
-
(2003)
Mater Sci Semicond Process
, vol.6
, pp. 85-92
-
-
Weide-Zaage, K.1
Dalleau, D.2
Yu, X.3
-
5
-
-
50249104192
-
-
Gotuaco M, Lee PW, et al. The case for CVD low-k technology. Semiconductorfabtech 15, Sec. 6 "Wafer Processing"; 2001. p. 179-83.
-
Gotuaco M, Lee PW, et al. The case for CVD low-k technology. Semiconductorfabtech 15, Sec. 6 "Wafer Processing"; 2001. p. 179-83.
-
-
-
-
6
-
-
0037674766
-
-
Wang G, Groothuis S, Ho PS. Effect of packaging on interfacial cracking in Cu/low k damascene structures. In: Proceedings of conference on IEEE/ECTC; 2003. p. 727-32.
-
Wang G, Groothuis S, Ho PS. Effect of packaging on interfacial cracking in Cu/low k damascene structures. In: Proceedings of conference on IEEE/ECTC; 2003. p. 727-32.
-
-
-
-
7
-
-
50249153284
-
-
ANSYS®, Inc. Software products, multiphysics, ANSYS, Inc. Southpointe, Canonsburg (PA), USA.
-
ANSYS®, Inc. Software products, multiphysics, ANSYS, Inc. Southpointe, Canonsburg (PA), USA.
-
-
-
-
8
-
-
85001139408
-
-
Waeterloos JJ, Struyfield H. Integration feasibility of porous SiLk semiconductor dielectric. In: Proceedings of IEEE interconnect technology conference; 2001. p. 253-4.
-
Waeterloos JJ, Struyfield H. Integration feasibility of porous SiLk semiconductor dielectric. In: Proceedings of IEEE interconnect technology conference; 2001. p. 253-4.
-
-
-
-
9
-
-
50249157803
-
Black diamond - a low k dielectric for Cu damascene applications
-
MRS
-
Yau W.-F., Lu Y.-C., et al. Black diamond - a low k dielectric for Cu damascene applications. AMC (1999) 379-386 MRS
-
(1999)
AMC
, pp. 379-386
-
-
Yau, W.-F.1
Lu, Y.-C.2
-
10
-
-
0034498614
-
Development of a low-dielectric constant polymer for the fabrication of integrated circuit interconnect
-
Martin Steven J., Godschalk James P., et al. Development of a low-dielectric constant polymer for the fabrication of integrated circuit interconnect. Adv Mater 12 23 (2000) 1769-1778
-
(2000)
Adv Mater
, vol.12
, Issue.23
, pp. 1769-1778
-
-
Martin Steven, J.1
Godschalk James, P.2
|