Thermo-mechanical modeling of process induced stress: Layout effect on stress voiding phenomena

AIP Conference Proceedings

Volumn 817, Issue , 2006, Pages 254-261

  Fiori, V ^a   Verrier, S ^a   Orain, S ^b   Girault, V ^a  

^a STMICROELECTRONICS   (France)

^b NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Bond over active; Finite element simulation; Interconnect reliability; Mechanical modeling; Stress gradient; Stress migration

Indexed keywords

EID: 33751248750     PISSN: 0094243X     EISSN: 15517616     Source Type: Conference Proceeding    
DOI: 10.1063/1.2173557     Document Type: Conference Paper

References (8)

1. S. Groothuis, R. Meade, Microelectronics and Electron Devices, 2005. WMED '05. 2005 IEEE Workshop on April 15, 2005 pp. 45 - 48.
2. C.J. Zhai, H.W. Yaho, Reliability Physics Symposium Proceedings, 2004. 42nd Annual. 2004 IEEE International 25-29 April 2004pp. 234 - 239.
3. K.Weide-Zaage, Void formation in a copper-via-structure depending on the stress free temperature and metallization geometry, Thermal and Mechanical Simulation and Experiments in Microelectronics and Microsystems, 2004. Proc. EuroSimE 2004. pp. 367 - 372.
4. S. Orain et al., FEM-based method to determinate mechanical stress evolution during process flow in microelectronics, application to stress-voiding, Proc. EuroSimE conference, 2004, pp. 47-52.
5. T. Hoffmann, V. Senez, Internal report, Mechanical analysis of the HCMOS9 Technology, 2000.
6. P. Flinn, "Mechanical stress in VLSI interconnections: Origins, effects, measurements and modeling", MRS Bulletin, November 1995, pp. 71-73.
7. J. P. Hirth, "Analysis of cavity nucleation in solids subjected to external and internal stresses", Acta Metall., Vol. 33, No. 3 (1985), pp. 359-368.
8. P.A. Flinn, Stress-induced void formation in Metal Lines, MRS Bulletin, Dec.1993, pp. 26-35.