Maximum power-up current estimation in combinational CMOS circuits

Proceedings of the Mediterranean Electrotechnical Conference - MELECON

Volumn 2006, Issue , 2006, Pages 70-73

  Sagahyroon, Assim ^a   Aloul, Fadi ^a  

^a AMERICAN UNIVERSITY OF SHARJAH   (United Arab Emirates)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGER PROGRAMMING; LEAKAGE CURRENTS; LINEAR PROGRAMMING; MICROPROCESSOR CHIPS; TRANSISTORS;

BOOLEAN SATISFIABILITY; CURRENT ESTIMATION; POWER-UP CURRENT; SLEEP MODE;

CMOS INTEGRATED CIRCUITS;

EID: 34047131618     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (25)

1. F. Aloul, A. Ramani, I. Markov, and K. Sakallah, "Generic ILP versus Specialized 0-1 ILP: An Update," in Proc. of the Int'l Conf. on Computer-Aided Design (ICCAD), 450-457, 2002.
2. P. Barth, "A Davis-Putnam based Enumeration Algorithm for Linear Pseudo-Boolean Optimization," Technical Report MPI-I-95-2-003, Max-Planck-Institut Für Informatik, 1995.
3. R. J. Bayardo Jr. and R. C. Schrag, "Using CSP Look-Back Techniques to Solve Real World SAT Instances," in National Conference on Artificial Intelligence (AAAI), 203-208, 1997.
4. A. Biere, A. Cimatti, E. Clarke, M. Fujita, and Y. Zhu, "Symbolic Model Checking using SAT procedures instead of BDDs", in Proc. of the Design Automation Conf. (DAC), 317-320, 1999.
5. P. Bjesse and K. Claessen, "SAT-based Verification Without State Space Traversal", in Proc. of Formal Methods in CAD, 372-389, 2000.
6. D. Chai and A. Kuehlmann, "A fast pseudo-boolean constraint solver," in Proc. of the Design Automation Conference (DAC), 830-835, 2003.
7. N. Creignou, S. Kanna, and M. Sudan, "Complexity Classifications of Boolean Constraint Satisfaction Problems", in SIAM Press, 2001.
8. M. Davis, G. Logemann, and D. Loveland, "A Machine Program for Theorem Proving," in Comm. of the ACM, 5(7), 394-397, 1962.
9. H. Dixon and M. Ginsberg, "Inference Methods for a Pseudo-Boolean Satisfiability Solver," in National Conference on Artificial Intelligence (AAAI), 635-640, 2002.
10. E. Goldberg and Y. Novikov, "BerkMin: A fast and robust SAT-solver," in Proc. of the Design Automation and Test Conference in Europe (DATE), 142-149, 2002.
11. ILOG CPLEX, http://www.ilog.com/products/cplex
12. F. Lei and L. He, "Maximum current estimation considering power gating," in Proc. of Intl. Symp. on Physical Design (ISPD), 222-227, 2001.
13. F. Lei, L. Hei, and K. Saluja, "Estimation of maximum power-up current," in ASPDAC, 51-58, 2002.
14. J. Marques-Silva and K. Sakallah, "GRASP: A Search Algorithm for Propositional Satisfiability", in IEEE Trans. on Computers, (48)5, 506-521, 1999.
15. MCNC Benchmarks, http://www.cbl.ncsu.edu/CBL_Docs/Bench.htm
16. S. Memik and F. Fallah, "Accelerated Boolean Satisfiability-Based Scheduling of Control/Data Flow Graphs for High-Level Synthesis", in Proc. of the Int'l Conf. on Computer Design, 2002.
17. M. Moskewicz, C. Madigan, Y. Zhao, L. Zhang, and S. Malik, "Chaff: Engineering an Efficient SAT Solver," in Proc. of the Design Automation Conference (DAC), 530-535, 2001.
18. MCNC benchmarks, http://www.cbl.ncsu.edu/CBL_Docs/Bench.html
19. G. Nam, F. Aloul, K. Sakallah, and R. Rutenbar, "A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints," in Proc. of Intl. Symp. on Physical Design (ISPD), 222-227, 2001.
20. M. Pedram, "Power minimization in IC design: principles and applications," ACM Trans. on Design Automation of Electronic Systems, 1(1), 3-56, 1996.
21. E. Sentovich et. al, "SIS: A System for Sequential Circuit Synthesis," Univ of California-Berkeley, UCB/ERL M92/41, 1992.
22. J. Silva and K. Sakallah, "Boolean satisfiability in electronic design automation," in Proc. of the Design Automation Conference (DAC), 675-680, 2000.
23. H. Sheini and K. Sakallah, "Pueblo: A Modern Pseudo-Boolean SAT Solver," in Proc. of the Design Automation and Test Conference in Europe (DATE), vol. 2, 684-685, 2005.
24. J. Whittemore, J. Kim, and K. Sakallah, "SATIRE: A New Incremental Satisfiability Engine," in Proc. of the Design Automation Conference (DAC), 542-545, 2001.
25. H. Zhang, "SATO: An Efficient Propositional Prover", in Proc. of the Int'l Conference on Automated Deduction, 272-275, 1997.