Transistor level automatic layout generator for non-complementary CMOS Cells

2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC

Volumn , Issue , 2007, Pages 116-121

  Ziesemer, Adriel ^a   Lazzari, Cristiano ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

[No Author keywords available]

Indexed keywords

CELLS; CYTOLOGY; INTEGER PROGRAMMING; LINEAR PROGRAMMING; LINEARIZATION; LSI CIRCUITS; MARINE BIOLOGY; PROGRAMMABLE LOGIC CONTROLLERS;

AUTOMATIC LAYOUT; CIRCUIT STRUCTURES; CMOS CELLS; DIFFUSION GAPS; EXACT METHODS; INTEGER LINEAR PROGRAMMING; INTERNAL CONNECTIONS; INTERNATIONAL CONFERENCES; LINEAR MATRICES; NET LIST; PLACEMENT ALGORITHMS; RUN TIMES; TRANSISTOR LEVELS; TRANSISTOR SIZING; VERY LARGE-SCALE INTEGRATION; WIDTH REDUCTION; WIRE LENGTHS;

CMOS INTEGRATED CIRCUITS;

EID: 50149093104     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSISOC.2007.4402483     Document Type: Conference Paper

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