XPRESS: A cell layout generator with integrated transistor folding

Proceedings of European Design and Test Conference

Volumn , Issue , 1996, Pages 393-400

  Gupta, Avaneendra ^a   The, Siang Chun ^a   Hayes, John P ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SOFTWARE; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT;

INTEGRATED TRANSISTOR FOLDING; SOFTWARE PACKAGE XPRESS; UNRESTRICTED CIRCUIT STRUCTURES;

CMOS INTEGRATED CIRCUITS;

EID: 0029736618     PISSN: 10661409     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (21)