Optimal 2-D cell layout with integrated transistor folding

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1998, Pages 128-135

  Gupta, Avaneendra ^a   Hayes, John P ^a  

^a CADENCE DESIGN SYSTEMS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; CONSTRAINT THEORY; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; MATHEMATICAL MODELS; TRANSISTORS;

INTEGRATED TRANSISTOR FOLDING;

COMPUTER AIDED DESIGN;

EID: 0032308186     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/288548.288590     Document Type: Conference Paper

References (16)