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Volumn , Issue , 1997, Pages 327-332
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CELLERITY: a fully automatic layout synthesis system for standard cell libraries
a a a a a a a |
Author keywords
[No Author keywords available]
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Indexed keywords
DIODES;
GATES (TRANSISTOR);
PERFORMANCE;
STANDARDS;
TECHNOLOGY;
TRANSISTORS;
AUTOMATIC LAYOUT SYNTHESIS;
STANDARD CELL;
TRANSISTOR FOLDING;
INTEGRATED CIRCUIT LAYOUT;
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EID: 0030646144
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (46)
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References (23)
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