Exact minimum-width transistor placement for dual and non-dual CMOS cells

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E88-A, Issue 12, 2005, Pages 3485-3491

  Iizuka, Tetsuya ^a,b   Ikeda, Makoto ^a,b,c   Asada, Kunihiro ^a,b,d,e  

^a UNIVERSITY OF TOKYO   (Japan)

^b IEEE

^c IPSJ   (Japan)

^d VDEC   (Japan)

^e IEEJ   (Japan)

Author keywords

Boolean satisfiability; Exact minimum width transistor placement; Non dual CMOS cells

Indexed keywords

BOOLEAN ALGEBRA; CMOS INTEGRATED CIRCUITS; PROBLEM SOLVING; STANDARDS;

BOOLEAN SATISFIABILITY; EXACT MINIMUM-WIDTH TRANSISTOR PLACEMENT; INDUSTRIAL STANDARD; NON-DUAL CMOS CELL;

TRANSISTORS;

EID: 29144507056     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e88-a.12.3485     Document Type: Article

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