High speed layout synthesis for minimum-width CMOS logic cells via Boolean Satisfiability

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2004, Pages 149-154

  Iizuka, Tetsuya ^a   Ikeda, Makoto ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATION; BOOLEAN ALGEBRA; INTEGER PROGRAMMING; LOGIC CIRCUITS; MOSFET DEVICES; RANDOM ACCESS STORAGE; SIMULATED ANNEALING; VLSI CIRCUITS;

BOOLEAN SATISFIABILITY; CELL GENERATION TOOL; CMOS LOGIC CELLS; LAYOUT GENERATION SYSTEMS;

CMOS INTEGRATED CIRCUITS;

EID: 2442618327     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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