RMPI: Message passing on multicore processors with on-chip interconnect

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 4917 LNCS, Issue , 2008, Pages 22-37

  Psota, James ^a   Agarwal, Anant ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ABSTRACTING; APPLICATION PROGRAMMING INTERFACES (API); CHLORINE COMPOUNDS; ELECTRIC NETWORK TOPOLOGY; HIGH PERFORMANCE LIQUID CHROMATOGRAPHY; INTERCONNECTION NETWORKS; MESSAGE PASSING; OPTICAL INTERCONNECTS; STANDARDIZATION; STANDARDS;

CLUSTER SYSTEMS; EMBEDDED ARCHITECTURES; INTERNATIONAL CONFERENCES; LEGACY APPLICATIONS; MEMORY FOOTPRINTS; MESSAGE-PASSING COMMUNICATION; MPI IMPLEMENTATION; MULTI CORES; MULTI-CORE PROCESSORS; NETWORK INTERFACES; ON-CHIP INTERCONNECTS; ON-CHIP NETWORKS; PARALLEL TASKS; PERFORMANCE SCALABILITY; PROCESSOR CORES; PROGRAMMING INTERFACES; PROGRAMMING MODELS; STANDARD ARCHITECTURE;

PROGRAM COMPILERS;

EID: 50049099419     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-540-77560-7_3     Document Type: Conference Paper

References (34)

1. Intel pentium d, http://www.intel.com/products/processor/pentium_d/
2. Moore's law 40th anniversary, http://www.intel.com/technology/mooreslaw/ index.htm
3. The multicore association communications api, http://www.multicore- association.org/workgroup/ComAPI.html
4. Transputer reference manual. Prentice Hall International (UK) Ltd. Hertfordshire, UK (1998)
5. Borkar, S., Cohn, R., Cox. G., Gleason, S., Gross, T., Kung, H.T., Lam, M., Moore, B., Peterson, C., et al.: iwarp: An integrated solution to high-speed parallel computing. In: Proceedings of Supercomputing (1998)
6. Bums, G., Daoud, R., Vaigl, J.: LAM: An Open Cluster Environment for MPI. In: Proceedings of Supercomputing Symposium, pp. 379-386 (1994)
7. Espasa, et al.: Tarantula: A Vector Extension to the Alpha Architecture. In: ISCA, pp. 281-292 (2002)
8. T.J., et al.: POWER4 system microarchitecture. IBM Journal of Research and Development 46(1), 5-25 (2002)
9. Forum, M.: A message passing interface standard. Technical report. University of Tennessee, Knoxville(1994)
10. Forum, M.P.I.: Mpi: A message-passing interface standard (1995), http://www.mpi-forum.org/docs/mpi-11-html/mpi-report.html
11. Gabriel, E., Fagg, G.E., Bosilca, G., Angskun, T., Dongarra, J.J., Squyres, J.M., Sahay, V., Kambadur, P., Barrett, B., Lumsdaine, A., Castain, R.H., Daniel, D.J., Graham, R.L., Woodall, T.S.: Open MPI: Goals, concept, and design of a next generation MPI implementation. In: Proceedings, 11th European PVM/MPI Users' Group Meeting, Budapest, Hungary, pp. 97-104 (September 2004)
12. Gordon, M.I., Thies, W., Karczmarek, M., Lin, J., Meli, A.S., Lamb, A.A., Leger, C., Wong, J., Hoffmann, H., Maze, D., Amarasinghe, S.: A Stream Compiler for Communication-Exposed Architectures. In: Conference on Architectural Support for Programming Languages and Operating Systems, pp. 291-303 (2002)
13. Griffin, P.: CFlow. Master's thesis. Lab for Computer Science, MIT (2005)
14. Gropp, W., Huss-Lederman, S., et al.: MPI: The Complete Reference, vol. 2. The MIT Press, Cambridge (1998)
15. Gropp, W.D., Lusk, E.: User's Guide for mpich, a Portable Implementation of MPI. In: ANL-96/6. Mathematics and Computer Science Division, Argonne National Laboratory (1996)
16. Hinrichs, S., Kosak, C., O'Hallaron, D., Stricker, T., Take, R.: An architecture for optimal all-to-all personalized communication. In: Proceedings of Symposium on Parallelism in Algorithms and Architectures (1994)
17. Karamcheti, V., Chien, A.A.: Software overhead in messaging layers: Where does the time go? In: Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, California, pp. 51-60 (1994)
18. Kozyrakis, C.E., Patterson, D.: A new direction for computer architecture research. Journal of the ACM (1997)
19. Kubiatowicz, J.: Integrated Shared-Memory and Message-Passing Communication in the Alewife Multiprocessor. PhD thesis, MIT (1998)
20. Lee, W., Barua, R., Frank, M., Srikrishna, D., Babb, J., Sarkar, V., Amarasinghe, S.: Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine. In: Proceedings of the Eighth ACM Conference on Architectural Support for Programming Languages and Operating Systems, San Jose, CA, pp. 46-57 (October 1998)
21. Mai, K., Paaske, T., Jayasena, N., Ho, R., Dally, W., Horowitz, M.: Smart memories: A modular reconfigurable architecture. In: Proceedings of the 27th International Symposium on Computer Architecture, pp. 161-170 (2000)
22. Mai, et al.: Smart Memories: A Modular Reconfigurable Architecture. In: ISCA (2000)
23. Nagarajan, R., Sankaralingam, K., Burger, D., Keckler, S.W.: A design space evaluation of grid processor architectures. In: International Symposium on Microarchitecture (MICRO) (2001)
24. Pacheco, P.S.: Parallel Programming with MPI. Morgan Kaufmann Publishers, San Francisco (1997)
25. Psota, J.: rMPI: An MPI-Compliant Message Passing Library for Tiled Architectures. Master's thesis, Lab for Computer Science, MIT (2005), http://cag.lcs.mit.edu/jim/publications/ms.pdf:
26. Quinn, M.J.: Parallel Programming in C with MPI and OpenMP. McGraw Hill, New York (2004)
27. Gropp, W., Huss-Lederman, S., et al.: MPI: The Complete Reference. The MIT Press, Cambridge (1998)
28. Squyres, J.M., Lumsdaine, A.: A Component Architecture for LAM/MPI. In: Dongarra. J.J., Laforenza, D., Orlando, S. (eds.) EuroPVM/MPI 2003. LNCS, vol. 2840, pp. 379-387. Springer, Heidelberg (2003)
29. Swanson, S., Michelson, K., Schwerin, A., Oskin, M.: Wavescalar. In: In the 36th Annual International Symposium on Microarchitecture (MICRO-36) (2003)
30. Taylor, M.B.: The Raw Processor Specification, ftp://ftp.cag.lcs.mit.edu/ pub/raw/documents/RawSpec99.pdf:
31. Taylor, et al.: The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs. IEEE Micro, 25-35 (March 2002)
32. Taylor, et al.: Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures. In: HPCA (2003)
33. Taylor, et al.: Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams. In: ISCA (2004)
34. William Gropp, A.S., Lusk. E.: A high-performance, portable implementation of the mpi message passing interface standard, http://www-unix.mcs.anl.gov/mpi/jmpich/papers/mpicharticle/paper.html