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Volumn , Issue , 2007, Pages 222-226

3D embedding and interconnection of ultra thin (< 20 μm) silicon dies

Author keywords

[No Author keywords available]

Indexed keywords

COPPER; ELECTRIC CONNECTORS; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONICS PACKAGING; METALS; NONMETALS; OPTICAL DESIGN; SILICON; TECHNOLOGY;

EID: 50049088522     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2007.4469735     Document Type: Conference Paper
Times cited : (27)

References (9)
  • 1
    • 50049120946 scopus 로고    scopus 로고
    • E. Beyne,Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits, IEDM 2001, pp. 23.3.1-23.3-4.
    • E. Beyne,"Technologies for very high bandwidth electrical interconnects between next generation VLSI circuits", IEDM 2001, pp. 23.3.1-23.3-4.
  • 2
    • 33947654392 scopus 로고    scopus 로고
    • 3-D integration is the way to go
    • March
    • E. Beyne, "3-D integration is the way to go", Advanced Packaging, March 2007, pp. 18.
    • (2007) Advanced Packaging , pp. 18
    • Beyne, E.1
  • 3
    • 50049106646 scopus 로고    scopus 로고
    • Chip embedded wafer level packaging technology for stacked RF-SiP application
    • Chien-Wei chien et al., "Chip embedded wafer level packaging technology for stacked RF-SiP application", IEEE ECTC, 2007, pp. 49-53.
    • (2007) IEEE ECTC , pp. 49-53
    • Chien-Wei chien1
  • 4
    • 35348823057 scopus 로고    scopus 로고
    • Chip-last embedded active for systm-on package
    • Baik-Woo Lee et al., "Chip-last embedded active for systm-on package", IEEE ECTC, 2007, pp. 292-298.
    • (2007) IEEE ECTC , pp. 292-298
    • Lee, B.-W.1
  • 6
    • 34547375250 scopus 로고    scopus 로고
    • 3D chip stacking technology with low-volume lead free interconnections
    • K. Sakuma et al, "3D chip stacking technology with low-volume lead free interconnections", IEEE ECTC, 2007, pp. 627-632.
    • (2007) IEEE ECTC , pp. 627-632
    • Sakuma, K.1
  • 7
    • 84877079081 scopus 로고    scopus 로고
    • wafer-level temporary bonding/debonding for thin wafer handling applications
    • March
    • K. de Munck et al., "wafer-level temporary bonding/debonding for thin wafer handling applications", IMAPS, March 2006.
    • (2006) IMAPS
    • de Munck, K.1
  • 9
    • 0037281908 scopus 로고    scopus 로고
    • Ultra thin ICs and MEMS elements: Techniques for wafer thinning stress-free separation, assembly and interconnection
    • M. Feil et al., "Ultra thin ICs and MEMS elements: techniques for wafer thinning stress-free separation, assembly and interconnection", Microsystem Technologies, vol. 9, 2003, pp. 176-182.
    • (2003) Microsystem Technologies , vol.9 , pp. 176-182
    • Feil, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.