Hierarchical Soft Error Estimation Tool (HSEET)

Proceedings of the 9th International Symposium on Quality Electronic Design, ISQED 2008

Volumn , Issue , 2008, Pages 680-683

  Ramakrishnan, K ^a   Rajaraman, R ^a   Vijaykrishnan, N ^a   Xie, Y ^a   Irwin, M J ^a   Unlu, K ^b  

^a The Pennsylvania State University   (United States)

^b INTEL TECHNOLOGY INDIA PVT LTD   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ANALYSIS RESULTS; BASIC BLOCKS; COMBINATIONAL CIRCUITS; CURRENT GENERATION; ELECTRONIC DESIGNS; HIERARCHICAL ARCHITECTURES; INTERNATIONAL SYMPOSIUM; NANO-METER REGIMES; PARTIAL PRODUCTS; PROBABILITY THEORY; RUN-TIME; SOFT ERROR RATES; SOFT ERRORS;

ELECTRONICS ENGINEERING; ERROR ANALYSIS; ERROR CORRECTION; ESTIMATION; MICROPROCESSOR CHIPS; NETWORKS (CIRCUITS); RISK ASSESSMENT;

ARCHITECTURAL DESIGN;

EID: 49949090259     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2008.4479819     Document Type: Conference Paper

References (22)

1. R. Baumann "Soft errors in advanced computer systems" IEEE D&T,22(3),May 2005.
2. R. C. Baumann, "Soft errors in advanced semiconductor devices-part I: the three radiation sources", IEEE Tran. on Device and Materials Reliability,Vol:1 Issue:1, Mar 2001.
3. P. Hazucha et.al, "Impact of CMOS Technology Scaling on the Atmospheric Neutron Soft Error Rate", IEEE Tran. on Nucl. Science, Vol. 47, No. 6, Dec 2000.
4. P. Shivakumar et.al, "Modeling the effect of technology trends on the soft error rate of combinational logic", In Proc. of DSN, June 2002.
5. L. W. Massengill etal, "Single event upset cross-section modeling in combinational CMOS logic circuits," In Jrl of Rad. Effects,vol. 16,no. 1,1998.
6. C. Zhao et.al, "A scalable soft spot analysis methodology for noise effects in nanometer circuits", In Proc. of DAC,2004.
7. M. Zhang et;al, "A Soft Error Rate Analysis (SERA) Methodology", In Proc. of ICCAD,2004.
8. Y. S. Dhillon etl.al, "Soft-Error tolerance analysis and optimization of nanometer circuits", In Proc. of DATE,2005.
9. B. Zhang et.al, "FASER:Fast Analysis of soft error susceptibility for cell-based designs" InProc. of ISQED,2006.
10. R. R. Rao etal, "An efficient static algorithm for computing the soft error rates of combinational circuits" In Proc. of DATE,2006.
11. R. Rajaraman et.al, "SEAT-LA: A Soft Error Analysis Tool for Combinational Logic", In Proc.of VLSID,2006.
12. S. Krishnaswamy, et.al, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices", In Proc. of DATE,2006.
13. N. M. Zivanov et.al, "MARS-C: Modeling and Reduction of Soft Errors in Combinational Circuits", In Proc. of DAC, 2006.
14. Predictive Tech. Model - http://www.eas.asu.edu/∼ptm/
15. http://www.micromagic. com/mmitools.html
16. A. Dharchoudhury et.al, "Fast timing simulation of transient faults in digital circuits", In Proc. of ICCAD, 1994.
17. JEDEC JESD89, "Measurement and reporting of alpha particles and terrestrial cosmic ray-induced soft errors in semiconductor devices", In JEDEC, Solid State Technology Association,2001.
18. Q. Zhou et.al, "Cost effective radiation hardening technique for combinational logic", In Proc. of ICCAD,2004.
19. H. S. Deogun et.al, "Gate-level mitigation techniques for Neutron induced soft error rate" In Proc. of ISQED,2005.
20. S. Ercolani et.al, "Estimate of signal probability in combinational logic networks", In Proc. of the ETC,1989.
21. J. Lamoureux et.al, "Activity Estimation for Field-Programmable Gate Arrays", In Proc. of FPL,2006.
22. http://www.cse.psu.edu/∼mdl/SE