Advances in quantum computing fault tolerance and testing

Proceedings of IEEE International Symposium on High Assurance Systems Engineering

Volumn , Issue , 2007, Pages 369-370

  Feinstein, David Y ^a   Nair, V S S ^a   Thornton, Mitchell A ^a  

^a SOUTHERN METHODIST UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECOHERENCE; FAULT MODELING; HIGH ASSURANCE SYSTEMS; INTERNATIONAL SYMPOSIUM; QUANTUM COMPUTING; QUANTUM LOGIC; RANDOM TESTING; TESTING AND FAULT-TOLERANCE;

DYNAMIC PROGRAMMING; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INDUSTRIAL ENGINEERING; QUANTUM CHEMISTRY; QUANTUM COMPUTERS; QUANTUM THEORY; RELIABILITY; SYSTEMS ENGINEERING; TECHNICAL PRESENTATIONS; TECHNOLOGY;

QUALITY ASSURANCE;

EID: 48349127792     PISSN: 15302059     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HASE.2007.16     Document Type: Conference Paper

References (5)

1. D. Y. Feinstein, Ph.D. Qualifier Examination Report, SMU, School of Engineering April 12, 2007.
2. M.A. Nielsen and I.L. Chuang, Quantum Computation and Qunatum Information, Cambridge University Press, 2000.
3. K.N. Patel, J.P. Hayes, and I.L. Markov, "Fault testing for reversible logic", In IEEE Trans, on CAD of IC and Systems, Vol. 23, No. 8, pp. 1220-1230, August 2004.
4. M.A. Perkowski, J. Biamonte, and M. Lukac, "Test generation and fault localization for quantum circuits", In ISMVL '05, pp 146-153, May 2005.
5. I. Polian, T. Fiehn, B. Becker, J. P. Hayes, "A Family of Logical Fault Models for Reversible Circuits" Proceedings 14th Asian Test Symposium, pp. 422-427, Dec. 2005.