Verifying the correctness of FPGA logic synthesis algorithms

ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA

Volumn , Issue , 2003, Pages 127-135

  Ratchev, Boris ^a   Hutton, Mike ^a   Baeckler, Gregg ^a   Van Antwerpen, Babette ^a  

^a ALTERA CORPORATION   (United States)

Author keywords

FPGA; Programmable logic; Synthesis; Test; Verification

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER AIDED DESIGN; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER SIMULATION; ERROR ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; STATISTICAL METHODS; VECTORS;

DIGITAL SYSTEMS; LOGIC SYNTHESIS ALGORITHMS; PROGRAMMABLE LOGIC;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0038349122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/611817.611837     Document Type: Conference Paper

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