Static property checking using ATPG v.s. BDD techniques

IEEE International Test Conference (TC)

Volumn , Issue , 2000, Pages 309-316

  Huang, Chung Yang ^a   Yang, Bwolen ^a   Tsai, Huan Chih ^a   Cheng, Kwang Ting ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DESIGN FOR TESTABILITY; FAILURE ANALYSIS; FORMAL LOGIC; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION;

AUTOMATIC TEST PATTERN GENERATORS; BDD; FORMAL VERIFICATION TECHNIQUES; FUNCTIONAL CORRECTNESS; STATIC PROPERTY CHECKING;

INTEGRATED CIRCUIT TESTING;

EID: 0034480137     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)