Correlation-based critical path predictors for low power microprocessors

Proceedings of the Innovative Architecture for Future Generation High-Performance Processors and Systems

Volumn 2003-January, Issue , 2003, Pages 11-18

  Chiyonobu, Akihiro ^a   Sato, Toshinori ^a,b   Arita, Itsujiro ^c  

^a Department of Artificial Intelligence ^*  (Japan)

^b KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

^c KYUSHU SANGYO UNIVERSITY   (Japan)

Author keywords

Critical path; Low power; Microprocessor

Indexed keywords

ENERGY EFFICIENCY; MICROPROCESSOR CHIPS;

CRITICAL PATHS; FUTURE RESEARCH DIRECTIONS; INSTRUCTION CRITICALITIES; LOW POWER; LOW POWER MICROPROCESSORS; PROCESSOR PERFORMANCE;

COMPUTER ARCHITECTURE;

EID: 84945563295     PISSN: 15373223     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IWIA.2003.1262778     Document Type: Conference Paper

References (12)

1. D. Burger, T. M. Austin: "The SimpleScalar Tool Set, Version 2.0", Technical Report CS-TR-97-1342, Computer Science Department, University of Wisconsin Madison, June 1997.
2. A. Chiyonobu: "Study on Critical Path Predictors for a Low Power Processor Architecture", Bachelor's Thesis, Kyushu Institute of Technology, February 2002 (in Japanese).
3. A. Chiyonobu, T. Sato, I. Arita: "A Proposal of Critical Path Predictors for Low Power Processor Architecture", 15th Summer United Workshop on Parallel, Distributed, and Cooperative Processing, August 2002 (in Japanese).
4. B. Fileds, S. Rubin, R. Blodik: "Focusing Processor Policies via Critical-Path Prediction", 28th International Symposium on Computer Architecture, July 2001.
5. M. Johnson: "Superscalar Microprocessor Design", Prentice Hall, 1991.
6. R. Kobayashi, H. Ando, T. Shimada: "Instruction-Issue Mechanism for a Clustered Superscalar Processor Focusing on a Critical Path in a Data Flow Graph", 13th Joint Symposium on Parallel Processing, June 2001 (in Japanese).
7. R. Pyreddy, G. Tyson: "Evaluating Design Tradeoffs in Dual Pipelines", Workshop on Complexity-Effective Design, June 2001.
8. F. Saito, H. Yamana: "The Latest Technical Trends in Speculative Execution", IPSJ SIG Notes, 2001-ARC-145-11, November 2001 (in Japanese).
9. T. Sato, T. Koushiro, A. Chiyonobu, I. Arita: "Power and Performance Fitting in Nanometer Design", 5th International Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems, January 2002.
10. T. Sato, A. Chiyonobu, I. Arita: "Energy Reduction via Critical Path Prediction", Workshop on Complexity-Effective Design held in conjunction with 29th International Symposium on Computer Architecture, May 2002.
11. J. S. Seng, E. S. Tune, D. M. Tullsen: "Reducing Power with Dynamic Critical Path Information", 34th International Symposium on Microarchitecture, December 2001.
12. E. Tune, D. Liang, D. M. Tullsen, B. Calder: "Dynamic Prediction of Critical Path Instructions", 7th International Symposium on High Performance Computer Architecture, January 2001.