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Volumn , Issue , 2008, Pages 843-848

A generic standard cell design methodology for differential circuit styles

Author keywords

[No Author keywords available]

Indexed keywords

CELL LIBRARIES; CIRCUIT DESIGNS; CIRCUIT TOPOLOGIES; CMOS TECHNOLOGIES; RAPID GENERATION; STANDARD CELLS; STANDARD-CELL DESIGNS; STANDARD-CELL LIBRARIES; SYSTEMATIC APPROACHES;

EID: 49749114826     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2008.4484779     Document Type: Conference Paper
Times cited : (19)

References (11)
  • 3
    • 0023401701 scopus 로고
    • A comparison of CMOS circuit techniques: Differential cascode voltage switch logic versus conventional logic
    • Aug
    • K. M. Chu and D. L. Pulfrey. A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic. IEEE Journal of Solid-State Circuits, 22(4):528-532, Aug. 1987.
    • (1987) IEEE Journal of Solid-State Circuits , vol.22 , Issue.4 , pp. 528-532
    • Chu, K.M.1    Pulfrey, D.L.2
  • 5
    • 0030174025 scopus 로고    scopus 로고
    • M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada. A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE Journal of Solid-State Circuits, 31(6):784-791, June 1996.
    • M. Mizuno, M. Yamashina, K. Furuta, H. Igura, H. Abiko, K. Okabe, A. Ono, and H. Yamada. A GHz MOS adaptive pipeline technique using MOS current-mode logic. IEEE Journal of Solid-State Circuits, 31(6):784-791, June 1996.
  • 8
    • 0030192342 scopus 로고    scopus 로고
    • Differential current switch logic: A low power DCVS logic family
    • Lille, France, July
    • D. Somasekhar and K. Roy. Differential current switch logic: a low power DCVS logic family. In Solid-State Circuits, IEEE Journal of, volume 31, pages 981-991, Lille, France, July 1996.
    • (1996) Solid-State Circuits, IEEE Journal of , vol.31 , pp. 981-991
    • Somasekhar, D.1    Roy, K.2
  • 9
    • 0032290311 scopus 로고    scopus 로고
    • LVDCSL: A high fan-in, high-performance, low-voltage differentialcurrent switch logic family
    • Dec
    • D. Somasekhar and K. Roy. LVDCSL: a high fan-in, high-performance, low-voltage differentialcurrent switch logic family. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(4):573-577, Dec. 1998.
    • (1998) IEEE Transactions on Very Large Scale Integration (VLSI) Systems , vol.6 , Issue.4 , pp. 573-577
    • Somasekhar, D.1    Roy, K.2
  • 10
    • 0000421830 scopus 로고
    • An MOS current mode logic (MCML) circuit for low-power sub-ghz processors
    • M. Yamashina and H. Yamada. An MOS current mode logic (MCML) circuit for low-power sub-ghz processors. IEICE Transaction on Electronics, E75-C(10):1181-1187, 1992.
    • (1992) IEICE Transaction on Electronics , vol.E75-C , Issue.10 , pp. 1181-1187
    • Yamashina, M.1    Yamada, H.2
  • 11
    • 0031189144 scopus 로고    scopus 로고
    • Low-power logic styles: CMOS versus pass-transistor logic
    • Neuchatel, Switzerland, July
    • R. Zimmermann and W. Fichtner. Low-power logic styles: CMOS versus pass-transistor logic. In Solid-State Circuits, IEEE Journal of, volume 32, pages 1079-1090, Neuchatel, Switzerland, July 1997.
    • (1997) Solid-State Circuits, IEEE Journal of , vol.32 , pp. 1079-1090
    • Zimmermann, R.1    Fichtner, W.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.