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Volumn 6, Issue 4, 1998, Pages 573-577

LVDCSL: A high fan-in, high-performance, low-voltage differential current switch logic family

Author keywords

Complementary metal oxide semiconductor (CMOS); Design; Dynamic logic circuit; High performance; Low power dissipation; Low voltage

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); INTERFACES (COMPUTER);

EID: 0032290311     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.736130     Document Type: Article
Times cited : (11)

References (10)
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    • Lee, W.1    Ko, U.2    Balsara, P.T.3
  • 2
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    • Chu, K.M.1    Pulfrey, D.L.2
  • 4
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    • Grotjohn, T.A.1    Hoefflinger, B.2
  • 5
    • 0024055838 scopus 로고
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    • S.-L. Lu, "Implementation of iterative networks with CMOS differential logic," IEEE J. Solid-State Circuits, vol. 23, pp. 1013-1017, Aug 1988.
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    • Lu, S.-L.1
  • 6
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    • Sept.
    • W. Chung-Yu and C. Kuo-Hsing, "Latched CMOS differential logic (LCDL) for complex high-speed VLSI," IEEE J. Solid-State Circuits, vol. 26, pp. 1324-1328, Sept. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 1324-1328
    • Chung-Yu, W.1    Kuo-Hsing, C.2
  • 7
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    • Evaluation of two-summand adders implemented in ECDL CMOS differential logic
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    • L. Shih-Lien and L. M. D. Ercegovac, "Evaluation of two-summand adders implemented in ECDL CMOS differential logic," IEEE J. Solid-State Circuits, vol. 26, pp. 1152-1160, Aug. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , pp. 1152-1160
    • Shih-Lien, L.1    Ercegovac, L.M.D.2
  • 8
    • 0026885667 scopus 로고
    • Design of self-checking circuits using DCVS logic: A case study
    • July
    • N. Kanopoulos et al., "Design of self-checking circuits using DCVS logic: A case study," IEEE Trans. Comput., vol. 41, pp. 891-896, July 1992.
    • (1992) IEEE Trans. Comput. , vol.41 , pp. 891-896
    • Kanopoulos, N.1
  • 9
    • 0027001693 scopus 로고
    • Design and implementation of a totally self-checking 16 multiplied by 16 bit array multiplier
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    • N. Kanopoulos and J. H. Carabetta, "Design and implementation of a totally self-checking 16 multiplied by 16 bit array multiplier," Integration, The VLSI J., vol. 14, no. 2, pp. 215-228, Dec 1992.
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  • 10
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    • Differential current switch logic: A low power DCVS logic family
    • July
    • D. Somasekhar and K. Roy, "Differential current switch logic: A low power DCVS logic family," IEEE J. Solid-State Circuits, vol. 31, pp. 981-991, July 1996.
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    • Somasekhar, D.1    Roy, K.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.