A GHz MOS adaptive pipeline technique using MOS current-mode logic

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 6, 1996, Pages 784-790

  Mizuno, Masayuki ^a,b   Yamashina, Masakazu ^a,b   Furuta, Koichiro ^a   Igura, Hiroyuki ^a,b   Abiko, Hitoshi ^a   Okabe, Kazuhiro ^a   Ono, Atsuki ^a   Yamada, Hachiro ^a  

^a NEC CORPORATION   (Japan)

^b IEEE

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PATH ANALYSIS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; LOGIC DESIGN; MOS DEVICES; SPURIOUS SIGNAL NOISE;

ADAPTIVE PIPELINE TECHNIQUE; CLOCK SKEW; EXCESSIVE POWER DISSIPATION; PROPAGATION DELAY TIME;

EMITTER COUPLED LOGIC CIRCUITS;

EID: 0030174025     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.509864     Document Type: Article

References (10)

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