A system-level Network-on-Chip simulation framework integrated with low-level analytical models

IEEE International Conference on Computer Design, ICCD 2006

Volumn , Issue , 2006, Pages 383-388

  Xi, Jinwen ^b   Zhong, Peixin ^a,b  

^a IEEE

^b Michigan State University   (United States)

Author keywords

NoC; Power model; SoC; SystemC

Indexed keywords

DISPENSERS; LARGE SCALE SYSTEMS; SPACE RESEARCH; WIRE;

ANALYTICAL MODELLING; COMPUTER DESIGNS; DEEP-SUBMICRON CMOS; DESIGN SPACE EXPLORATION; DESIGN STAGES; FAST SIMULATION; INTERNATIONAL CONFERENCES; LEVEL MODEL; MODELING FRAMEWORK; NETWORK ON CHIPS; NOC; OPTIMIZATION AND DESIGN; POWER ANALYSIS; POWER DISSIPATIONS; POWER MODEL; SIMULATION FRAMEWORK; SOC; SYSTEM LEVELS; SYSTEM PERFORMANCES; SYSTEMC; TEMPORAL GRANULARITY; TRAFFIC CONDITIONS;

ELECTRIC NETWORK TOPOLOGY;

EID: 49749113269     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2006.4380845     Document Type: Conference Paper

References (13)

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